A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide l...A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.展开更多
主要研究采用IBM公司SOI 0.18μm CMOS工艺设计应用于1.95 GHz WCDMA发射机的全集成线性功率放大器的设计方法。电路采用三级AB类放大器级联结构,模拟结果显示,在工作电压为2.5 V的情况下,CMOS射频功率放大器工作稳定,1 d B压缩点输出...主要研究采用IBM公司SOI 0.18μm CMOS工艺设计应用于1.95 GHz WCDMA发射机的全集成线性功率放大器的设计方法。电路采用三级AB类放大器级联结构,模拟结果显示,在工作电压为2.5 V的情况下,CMOS射频功率放大器工作稳定,1 d B压缩点输出功率约为30 d Bm,增益约为28 d B,最大功率增加效率(PAE)约为42%。展开更多
基金Supported by the National Natural Science Foundation of China under Grant Nos 61404014 and 61405018the Fundamental Research Funds for the Central Universities under Grant Nos CDJZR12160003 and 106112014CDJZR168801
文摘A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.
文摘主要研究采用IBM公司SOI 0.18μm CMOS工艺设计应用于1.95 GHz WCDMA发射机的全集成线性功率放大器的设计方法。电路采用三级AB类放大器级联结构,模拟结果显示,在工作电压为2.5 V的情况下,CMOS射频功率放大器工作稳定,1 d B压缩点输出功率约为30 d Bm,增益约为28 d B,最大功率增加效率(PAE)约为42%。
