Integrated power electronics module based on chip scale packaged power devices

High performance can be obtained for the integrated power electronics module（IPEM） by using a three-dimensional packaging structure instead of a planar structure. A three- dimensional packaged half bridge-IPEM （HB-IPEM）, consisting of two chip scale packaged MOSFETs and the corresponding gate driver and protection circuits, is fabricated at the laboratory. The reliability of the IPEM is controlled from the shape design of solder joints and the control of assembly process parameters. The parasitic parameters are extracted using Agilent 4395A impedance analyzer for building the parasitic parameter model of the HB- IPEM. A 12 V/3 A output synchronous rectifier Buck converter using the HB-IPEM is built to test the electrical performance of the HB-IPEM. Low voltage spikes on two MOSFETs illustrate that the three-dimensional package of the HB-IPEM can decrease parasitic inductance. Temperature distribution simulation results of the HB-IPEM using FLOTHERM are given. Heat dissipation of the solder joints makes the peak junction temperature of the chip drop obviously. The package realizes three-dimensional heat dissipation and has better thermal management.

Design of DC regulated power supply based on single chip microcomputer

A DC regulated power supply with numerical control based on single chip microcomputer （SCM） is designed. SCM is the main controller and output voltage o{ DC power supply can be set by keyboard. The analog voltage can be obtained through D/A converter （DAC0832） so that different voltages can be provided by operational amplifier. The output voltage varies from 0 V to 12 V with the incremental value of 0. 1 V. The actual output voltage is shown in the nixietube. This DC regulated power supply is characterized by simple structure and easy operation.

Ultrasonic power features of wire bonding and thermosonic flip chip bonding in microelectronics packaging

The driving voltage and current signals of piezoceramic transducer (PZT) were measured directly by designing circuits from ultrasonic generator and using a data acquisition software system. The input impedance and power of PZT were investigated by using root mean square (RMS) calculation. The vibration driven by high frequency was tested by laser Doppler vibrometer (PSV-400-M2). And the thermosonic bonding features were observed by scanning electron microscope (JSM-6360LV). The results show that the input power of bonding is lower than that of no load. The input impedance of bonding is greater than that of no load. Nonlinear phase, plastic flow and expansion period, and strengthening bonding process are shown in the impedance and power curves. The ultrasonic power is in direct proportion to the vibration displacement driven by the power, and greater displacements driven by high power (>5 W) result in welding failure phenomena, such as crack, break, and peeling off in wedge bonding. For thermosonic flip chip bonding, the high power decreases position precision of bonding or results in slippage and rotation phenomena of bumps. To improve reliability and precision of thermosonic bonding, the low ultrasonic power (about 1-5 W) should be chosen.

The Design of PSM-Based ECRH Power Supply Control System

Electron cyclotron resonance heating (ECRH) system is one of the most important Tokamak auxiliary heating methods. However, there are growing demands for ECRH system as the physical experiments progress which meanwhile adds the difficulty of designing and building the control system of its power source. In this paper, the method of designing a control system based on Single Chip Microcomputer (SCM) and Field Programmable Gate Array (FPGA) is introduced according to its main requirements. The experimental results show that the control system in this paper achieves the conversion of different working modes, gets exact timing, and realizes the failure protection in 10us thus can be used in the ECRH system.

Analysis and Research on Low-Cost and Non-Intrusive Power Metering Chip

Metering technology is one of the core technologies of the smart power grid. The overall metering solution and related products have a wide market space in the whole process of power production, which bring new opportunities for power distribution development from automation to intelligentialize, and provide technical supports for the power metering system platform. Because of the importance of metering products and their market demand, this paper focuses on the design of a simple power metering chip with low-cost, low-precision and non-invasive, so as to lay the foundation for the development and practical technology accumulation of power metering products. The design achieves low cost by reducing the acquisition accuracy, simplifying the collection and sampling methods. This paper studies the chip accuracy, sampling methods, collection methods, and the inference of the chip characteristics requirements.

Design of Efficient Router with Low Power and Low Latency for Network on Chip

The NoC consists of processing element (PE), network interface (NI) and router. This paper proposes a hybrid scheme for Netwok of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between routers. The main objective of this paper is to reduce the latency and power consumption of the network on chip architecture using wireless link between routers. In this paper, the power consumption is reduced by designing a low power router and latency is reduced by implementing a on-chip wireless communication as express links for transferring data from one subnet routers to another subnet routers. The average packet latency and normalized power consumption of proposed hybrid NoC router are analyzed for synthetic traffic loads as shuffle traffic, bitcomp traffic, transpose traffic and bitrev traffic. The proposed hybrid NoC router reduces the normalized power over the wired NoC by 12.18% in consumer traffic, 12.80% in AutoIndust traffic and 12.5% in MPEG2 traffic. The performance is also analyzed with real time traffic environments using Network simulator 2 tool.

Energy Efficient On-Chip Communications Implementation Based on Power Slacks

The quest for energy efficiency has growing importance in high performance many-core systems. However, in current practices, the power slacks, which are the differences observed between the input power budget and the actual power consumed in the many-core systems, are typically ignored, thus leading to poor energy efficiency. In this paper, we propose a scheme to effectively power the on-chip communications by exploiting the available power slack that is totally wasted in current many-core systems. As so, the demand for extra energy from external power sources （e.g., batteries） is minimized, which helps improve the overall energy efficiency. In essence, the power slack is stored at each node and the proposed routing algorithm uses a dynamic programming network to find the globally optimal path, along which the total energy stored on the nodes is the maximum. Experimental results have confirmed that the proposed scheme, with low hardware overhead, can reduce latency and extra energy consumption by 44% and 48%, respectively, compared with the two competing routing methods.

Design of Power Supply for On-line Monitoring System of Transmission Lines

This paper uses CT to gain the energy directly from the high-voltage transmission line, to address the problem of power supply for monitoring system in high voltage side of transmission line. The draw-out power coil can induce voltage from the transmission line, using single-chip microcomputer to analog and output PMW wave to control the charging module, provides a stable 3.4 V DC voltage to the load, and solve the problem of easy saturating of core. The power supply based on this kind of draw-out power coil has undergone the overall testing, and it is verified-showing that it can properly work in a non-saturated status within the current range of 50 - 1000 A, and provide a stable output. The equipment also design protection circuit to improve the reliability to avid the impacts of the impulse current or short-circuit current. It effectively solves the problem of power supply for On-line Monitoring System of Transmission.

Signal and Power Integrity Challenges for High Density System-on-Package

As the increasing desire for more compact,portable devices outpaces Moore’s law,innovation in packaging and system design has played a significant role in the continued miniaturization of electronic systems.Integrating more active and passive components into the package itself,as the case for system-on-package(SoP),has shown very promising results in overall size reduction and increased performance of electronic systems.With this ability to shrink electrical systems comes the many challenges of sustaining,let alone improving,reliability and performance.The fundamental signal,power,and thermal integrity issues are discussed in detail,along with published techniques from around the industry to mitigate these issues in SoP applications.

RESEARCH ON A REAL-TIME CONTROL SYSTEM OF LOW POWER DISSIPATION FOR CONTINUOUS CYCLIC PERITONEAL DIALYSIS(CCPD) CYCLER

A low power dissipation control system for continuous cyclic peritoneal dialysis (CCPD) cycler and its characteristics are reported. Combined withhemodialysis and renal transplantation, peritoneal dialysis is used mainly for thetreatment of renal failure. CCPD has been developed during 1980＇s. It provided automatic dialysis procedures during the night to avoid interruptions in patients＇dailyroutine. Furthermore,there is a remarkable decrease in peritonitis occurance usingCCPD. The control system is a critical part for CCPD cycler. The system is approvedto be reliable and flexible in practical experiments. When AC power failure,the system can still ensure the completion of dialysis.

Stepping Control Method of Linear Displacement Mechanism Driven by TRUM Based on PSoC

A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm.

Semiconductor Optical Amplifier and Gain Chip Used in Wavelength Tunable Lasers

The design concept of semiconductor optical amplifier(SOA)and gain chip used in wavelength tunable lasers(TL)is discussed in this paper.The design concept is similar to that of a conventional SOA or a laser;however,there are a few different points.An SOA in front of the tunable laser should be polarization dependent and has low optical confinement factor.To obtain wide gain bandwidth at the threshold current,the gain chip used in the tunable laser cavity should be something between SOA and fixed-wavelength laser design,while the fixed-wavelength laser has high optical confinement factor.Detailed discussion is given with basic equations and some simulation results on saturation power of the SOA and gain bandwidth of gain chip are shown.

Signal processing for PSoC based PIR motion detection

A signal processing scheme for a programmable system-on-chip(PSoC)based human body infrared tracking system is described.The purpose of this project is to convert the analog signal from a passive infrared(PIR)sensor to a digital signal which will be used to calculate the correct position of a human body.This paper covers the analog design with PSoC,the analog to digital conversion and the software to eliminate noise.

Development of Simulated Testbed for Electrical Power Subsystem of a Certain Kind of Satellite

In order to testify and examine the ability and correctness of an expert system for diagnosing the faults in the electrical power system of a certain kind of satellite, the authors have developed a simulated testbed according to the operational principle of the electrical power system. This paper takes the solar battery array as an instance to introduce the designing principle of its hardware circuits, and presents the methods to design the interface and the software program of the single-chip microprocessor system. The software scheme of the upper computer is introduced at the end of this paper. It has been proved that this simulated system could effectively achieve the complete functions coupled with the simple design by using of various mature techniques in the fields of electronic circuits, single-chip microprocessor and numerical emulation.

New Latency Model for Dynamic Frequency Scaling on Network-on-Chip

Modulating both the clock frequency and supply voltage of the network-on-chip （NoC） during runtime can reduce the power consumption and heat flux, but will lead to the increase of the latency of NoC. It is necessary to find a tradeoff between power consumption and communication latency. So we propose an analytical latency model which can show us the relationship of them. The proposed model to analyze latency is based on the M/G/1 queuing model, which is suitable for dynamic frequency scaling. The experiment results show that the accuracy of this model is more than 90%.

Energy-Efficient Scheduling Based on Task Migration Policy Using DPM for Homogeneous MPSoCs

Increasing the life span and efficiency of Multiprocessor System on Chip(MPSoC)by reducing power and energy utilization has become a critical chip design challenge for multiprocessor systems.With the advancement of technology,the performance management of central processing unit(CPU)is changing.Power densities and thermal effects are quickly increasing in multi-core embedded technologies due to shrinking of chip size.When energy consumption reaches a threshold that creates a delay in complementary metal oxide semiconductor(CMOS)circuits and reduces the speed by 10%–15%because excessive on-chip temperature shortens the chip’s life cycle.In this paper,we address the scheduling&energy utilization problem by introducing and evaluating an optimal energy-aware earliest deadline first scheduling(EA-EDF)based technique formultiprocessor environments with task migration that enhances the performance and efficiency in multiprocessor systemon-chip while lowering energy and power consumption.The selection of core andmigration of tasks prevents the system from reaching itsmaximumenergy utilization while effectively using the dynamic power management(DPM)policy.Increase in the execution of tasks the temperature and utilization factor(u_(i))on-chip increases that dissipate more power.The proposed approach migrates such tasks to the core that produces less heat and consumes less power by distributing the load on other cores to lower the temperature and optimizes the duration of idle and sleep times across multiple CPUs.The performance of the EA-EDF algorithm was evaluated by an extensive set of experiments,where excellent results were reported when compared to other current techniques,the efficacy of the proposed methodology reduces the power and energy consumption by 4.3%–4.7%on a utilization of 6%,36%&46%at 520&624 MHz operating frequency when particularly in comparison to other energy-aware methods for MPSoCs.Tasks are running and accurately scheduled to make an energy-efficient processor by controlling and managing the thermal effects on-chip and optimizing the energy consumption of MPSoCs.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

High power and high reliability GaN/InGaN flip-chip light-emitting diodes

High-power and high-reliability GaN/InGaN flip-chip light-emitting diodes （FCLEDs） have been demonstrated by employing a flip-chip design, and its fabrication process is developed. FCLED is composed of a LED die and a submount which is integrated with circuits to protect the LED from electrostatic discharge （ESD） damage. The LED die is flip-chip soldered to the submount, and light is extracted through the transparent sapphire substrate instead of an absorbing Ni/Au contact layer as in conventional GaN/InGaN LED epitaxial designs. The optical and electrical characteristics of the FCLED are presented. According to ESD IEC61000-4-2 standard （human body model）, the FCLEDs tolerated at least 10 kV ESD shock have ten times more capacity than conventional GaN/InGaN LEDs. It is shown that the light output from the FCLEDs at forward current 350mA with a forward voltage of 3.3 V is 144.68 mW, and 236.59 mW at 1.0A of forward current. With employing an optimized contact scheme the FCLEDs can easily operate up to 1.0A without significant power degradation or failure. The li.fe test of FCLEDs is performed at forward current of 200 mA at room temperature. The degradation of the light output power is no more than 9% after 1010.75 h of life test, indicating the excellent reliability. FCLEDs can be used in practice where high power and high reliability are necessary, and allow designs with a reduced number of LEDs.

基于PSoC的数字电子技术教学改革探索

把集数字可编程阵列、模拟可编程阵列和微处理器集为一体的可编程片上系统PSoC用于数字电子技术理论课程的辅助教学之中。基于PSoC设计数字电子技术综合设计实例,将数字电子技术课程的组合逻辑电路、数字逻辑电路、脉冲波形的产生、存储器可编程逻辑器件等主要知识点贯通于一起,通过少量的课时,在理论教学中融入生活实例设计,培养了学生设计与调试电路的能力,同时解决了理论课程枯燥乏味的问题,激发了学生学习兴趣。论文一方面通过PSoC将可编程技术和EDA技术贯穿于理论教学的始末,同时将LUT设计法、IP核设计以及注解法等设计方法引入到理论教学中,使学生尽早接触电子技术的前沿知识,拓宽了学生的学术视野。

基于PSoC的实验教学平台开发

可编程片上系统（PSoC）是一种新型芯片,它集控制器、数字、模拟常用模块于一身,具有小型化、集成化、高可靠性的特点,适用于电子系统设计与实验教学。设计并开发了一种基于PSoC的实验教学平台,由浅入深地为学生提供了多种类型的实验,如信号发生器实验、电子琴实验、电机测速实验、短信报警实验等,具有综合性、模块化、易于连线和调试的特点,方便学生熟悉并掌握PSoC技术,并能自己设计、验证PSoC实验。该实验教学平台在教学实践中应用效果良好。