Adaptive Digital Predistortion Schemes to Linearize RF Power Amplifiers with Memory Effects

To compensate for nonlinear distortion introduced by RF power amplifiers （PAs） with memory effects, two correlated models, namely an extended memory polynomial （EMP） model and a memory lookup table （LUT） model, are proposed for predistorter design. Two adaptive digital predistortion （ADPD） schemes with indirect learning architecture are presented. One adopts the EMP model and the recursive least square （RLS） algorithm, and the other utilizes the memory LUT model and the least mean square （LMS） algorithm. Simulation results demonstrate that the EMP-based ADPD yields the best linearization performance in terms of suppressing spectral regrowth. It is also shown that the ADPD based on memory LUT makes optimum tradeoff between performance and computational complexity.

ANALOG PREDISTORTION LINEARIZER ON REDUCING CORRECTED AMPLITUDE OVERSHOOT

This paper presents a dual-nonlinear branch linearizer for reducing the corrected amplitude overshoot of conventional single nonlinear branch linearizer. Theoretical analysis is carried out, the analysis is verified by simulation, and a prototype of Ka band 25.28~26.08 GHz dual nonlinear branch linearizer is achieved. It indicates that the corrected amplitude overshoot is less than 0.5 dB, the C/I3 improvement is more than 10 dB related to a single carrier IBO 9 dB, when it is linked and tested for 50 W spacebrone Travelling Wave Tube Amplifier(TWTA).

Robust Digital Predistortion for LTE/5G Power Amplifiers Utilizing Negative Feedback Iteration

A robust digital predistortion(DPD)technique utilizing negative feedback iteration is introduced for linearizing power amplifiers(PAs)in long term evolution(LTE)/5G systems.Different from the conventional direct learning and indirect learning structure,the proposed DPD suggests a two-step method to identify the predistortion.Firstly,a negative feedback based iteration is used to estimate the optimal DPD signal.Then the corresponding DPD parameters are extracted by forward modeling with the input signal and optimal DPD signal.The iteration can be applied to both single-band and dual-band PAs,which will achieve superior linear performance than the conventional direct learning DPD while having a relatively low computational complexity.The measurement is carried out on a broadband Doherty PA(DPA)with a 200 MHz bandwidth LTE signal at 2.1 GHz,and on a 5G DPA with two 10 MHz LTE signals at 3.4/3.6 GHz for validation in dual-band scenarios.

Digital Predistortion and Measurement Method

Digital PreDistortion(DPD)is a very useful method to improve the linearity of Power Amplifiers(PAs)for LTE and upcoming 5 G networks.As the spectrum resources are becoming more and more crowded,and the communications bandwidth are broader,the ACPR(Adjacent Channel Leakage Ratio)is very important to communication systems.DPD is one of the useful means for PA to reduce ACPR.This article demonstrates what DPD is and how DPD is achieved,the measurement of the Digital Distortion of a PA using a vector generator and vector analyzer,and the measurement results has been discussed.

Volterra series based predistortion for broadband RF power amplifiers with memory effects

RF power amplifiers （PAs） are usually considered as memoryless devices in most existing predistortion techniques. However, in broadband communication systems, such as WCDMA, the PA memory effects are significant, and memoryless predistortion cannot linearize the PAs effectively. After analyzing the PA memory effects, a novel predistortion method based on the simplified Volterra series is proposed to linearize broadband RF PAs with memory effects. The indirect learning architecture is adopted to design the predistortion scheme and the reeursive least squares algorithm with forgetting factor is applied to identify the parameters of the predistorter. Simulation results show that the proposed predistortion method can compensate the nonlinear distortion and memory effects of broadband RF PAs effectively.

A Strong Anti-Jamming Algorithm Based on FPGA for Estimating Loop Delay in Digital Predistortion System

At present what are the key points focused in the research of loop-delay estimation for the digital predistorter in the radio frequency （RF） power amplifier system is reducing its complexity of engineering realization and improving anti-jamming ability and computational speed. Besides, opening up its application scope should be contained. For these targets, a novel method including integer loop delay estimation and fractional part is proposed. The integer part applies amplitude-difference summation function and the fractional one adopts the method of finite impulse response （FIR） linear interpolation. The algorithm finds wide applications. What is more, strong anti-jamming ability and low complexity are also its merits. Simulation results support the above opinion. Digital predistortion （DPD） system based on this algorithm achieves good performance.

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve the linearity of the power amplifier(PA).As a result,there is a significant improvement in power-added efficiency(PAE)and linearity is achieved.The Ka-band PA is implemented in TSMC 65nm CMOS process.At 1.2V supply voltage,the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%.After linearization,the output power at the ldB compression point is increased by 2dBm,with efficient gain compensation performance.

A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

A transformer-based CMOS power amplifier （PA） is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter. The third harmonic of the power stage and driver stage can be cancelled out in a specific power region. The two-stage PA fabricated in a standard 0.18-#m CMOS process delivers 27.5 dBm with 27% PAE at the 1-dB compression point （PldB） and offers 21 dB gain. The PA achieves 5.5 % EVM and meets the spectrum mask at 20.5 dBm average power. Another conventional PA with a zero-cross-point of gm3 bias is also fabricated and compared to prove its good linearity and efficiency.

Linear Power Amplifier Modeling Based on Predistortion Technology

Different power amplifier （PA） models have their own effects on PA linearization. In this paper, the nonlinear characteristic of the radio frequency power amplifier （RF PA） is simulated based on the two models combining predistortion technology, and the nonlinear effects of the two models are analyzed, respectively. The simulation results show that Power Series model normalized mean square error （NMSE） is -37.8 dB, which is less than Power Series model -30.4 dB before loading predistortion technology. NMSE of the two systems are -23.4 dB and -26.0 dB respectively, while Saleh model compensates better than the Power Series model combing predistortion technology. The error vector magni- tude （EVM） of Power Series model is only 6.75%, whereas the Saleh model EVM is 9.99%, indicating that Power Series model can better describe the nonlinear characteristic of PA. It will have a positive effect on improving the power utilization of wireless communication system.

Low sampling rate technique based frequency-domain random demodulation for broadband digital predistortion

This paper proposes a combination technique of the frequency-domain random demodulation（FRD） and the broadband digital predistorter（DPD）. This technique can linearize the power amplifiers（PAs） at a low sampling rate in the feedback loop. Based on the theory of compressed sensing（CS）, the FRD method preprocesses the original signal using the frequency domain sampling signal with different stages through multiple parallel channels. Then the FRD method is applied to the broadband DPD system to restrict the sampling process in the feedback loop. The proposed technique is assessed using a 30 W Class-F wideband PA driven by a 20 MHz orthogonal frequency division multiplexing（OFDM） signal, and a 40 W Ga N Doherty PA driven by a 40 MHz 4-carrier long-term evolution（LTE） signal. The simulation and experimental results show that good linearization performance can be achieved at a lower sampling rate with about- 24 d Bc adjacent channel power ratio（ACPR） improvement by applying the proposed combination technique FRD-DPD. Furthermore, the performance of normalized mean square error（NMSE） and error vector magnitude（EVM） also has been much improved compared with the conventional technique.

Robust power amplifier predistorter by using memory polynomials

In memory polynomial predistorter design, the coefficient estimation algorithm based on normalized least mean square is sensitive to initialization parameters. A predistorter based on generalized normalized gradient descent algorithm is proposed. The merit of the GNGD algorithm is that its learning rate provides compensation for the independent assumptions in the derivation of NLMS, thus its stability is improved. Computer simulation shows that the proposed predistorter is very robust. It can overcome the sensitivity of initialization parameters and get a better linearization performance.

A Discrete Newton's Method for Gain Based Predistorter

Gain based predistorter (PD) is a highly effective and simple digital baseband predistorter which compensates for the nonlinear distortion of PAs. Lookup table (LUT) is the core of the gain based PD. This paper presents a discrete Newton’s method based adaptive technique to modify LUT. We simplify and convert the hardship of adaptive updating LUT to the roots finding problem for a system of two element real equations on athematics. And we deduce discrete Newton’s method based adaptive iterative formula used for updating LUT. The iterative formula of the proposed method is in real number field, but secant method previously published is in complex number field. So the proposed method reduces the number of real multiplications and is implemented with ease by hardware. Furthermore, computer simulation results verify gain based PD using discrete Newton’s method could rectify nonlinear distortion and improve system performance. Also, the simulation results reveal the proposed method reaches to the stable statement in fewer iteration times and less runtime than secant method.

Non-Overlapping Conditions to Enable Multi- Dimensional Behavioral Models/DPDs for Multi-Band or Non-Continuous Carrier Aggregation Systems

To linearize the multi.band PAs/transmitters, a serial of multi.band predistortion models based on multi.dimensional architecture have been proposed. However, most of these models work properly only for the signals whose harmonic and intermodulation products of carriers' non.overlap with the interested fundamental bands. In this paper, the non.overlapping conditions for dual.band and tri.band signals are derived and denoted in the form of closed.form expression. It can be used to verify whether a given dual.band/multi.band signals can be linearized properly by these multi.dimensional behavioral models. Also the conditions can be used to plan the frequency spacing and maximum bandwidth of a multi.band or non.continuous carrier aggregation signal. Several dual.band and triband signals were tested on the same PA, by employing 2.D DPD and 3.D DPD behavioral models. The measurement results show that the signals which don't satisfy the non.overlapping conditions cannot be linearized well by the multi.dimensional behavioral models which does not take the harmonic and intermodulation products of carriers' into account.

FPGA Implementation of a Power Amplifier Linearizer for an ETSI-SDR OFDM Transmitter

Most satellite digital radio （SDR） systems use orthogonal frequency-division multiplexing （OFDM） transmission, which means that variable envelope signals are distorted by the RF power amplifier （PA）. It is customary to back off the input power to the PA to avoid the PA nonlinear region of operation. In this way, linearity can be achieved at the cost of power efficiency. Another attractive option is to use a linearizer, which compensates for the nonlinear effects of the PA. In this paper, an OFDM transmitter conforming to European Telecommunications Standard Institute SDR Technical Specifications 2007-2008 was designed and implemented on a low-cost field-programmable gate array （FPGA） platform. A weakly nonlinear PA, operating in the L-band SDR frequency, was used for signal transmission. An adaptive linearizer was designed and implemented on the same FPGA device using digital predistortion to correct the undesired effects of the PA on the transmitted signal. Test results show that spectral distortion can be suppressed between 6-9 dB using the designed linearizer when the PA is driven close to its saturation region.

运放非理想特性的预畸变补尝

在有源滤波器的设计中一般都假定集成电路运算放大器是理想的。在工程设计中常常由于运算放大器的非理想特性,例如有限的带宽—增益乘积等使滤波器特性偏离设计值。

Design of a memory polynomial predistorter for wideband envelope tracking amplifiers

Efficiency and linearity of the microwave power amplifier are critical elements for mobile communication systems. A memory polynomial baseband predistorter based on an indirect learning architecture is presented for improving the linearity of an envelope tracing （ET） amplifier with application to a wireless transmitter. To deal with large peak-to-average ratio （PAR） problem, a clipping procedure for the input signal is employed. Then the system performance is verified by simulation results. For a single carrier wideband code division multiple access （WCDMA） signal of 16-quadrature amplitude modulation （16-QAM）, about 2% improvement of the error vector magnitude （EVM） is achieved at an average output power of 45.5 dBm and gain of 10.6 dB, with adjacent channel leakage ratio （ACLR） of -64.55 dBc at offset frequency of 5 MHz. Moreover, a three-carrier WCDMA signal and a third-generation （3G） long term evolution （LTE） signal are used as test signals to demonstrate the performance of the proposed linearization scheme under different bandwidth signals.

New predistorter using triangular memory polynomial for power amplifier of OFDM-based wireless broadband communication system

A triangular memory polynomial （TMP） predistorter is presented in this paper to linearize a power amplifier＇s nonlinear with memory effects. Compared with the traditional memory polynomial （MP） predistorter, the coefficients of TMP predistorter is reduced more than 75%, which can effectively decrease the implementation complexity. The coefficients of predistorter are directly extracted from an offline system identification process by an open-loop structure in our approach. Several signals with data rate 5 MHz, 10 MHz, 15 MHz and 20 MHz are used to verify the performance of the proposed predistorter. Experimental results show that the proposed TMP predistorter and the traditional MP predistorter almost have the same performance.

Performance of a recursive algorithm for polynomial predistorter design

In this article, based on least square estimation, a recursive algorithm for indirect learning structure predistorter is introduced. Simulation results show that of all polynomial predistorter nonlinear terms, higher-order （higher than 7th-order） nonlinear terms are so minor that they can be omitted in practical predistorter design. So, it is unnecessary to construct predistorter with higher-order polynomials, and the algorithm will always be stable. Further results show that even when 15th-order polynomial model is used, the algorithm is convergent after 10 iterations, and it can improve out-band spectrum of 20 MHz bandwidth signal by 64 dB, with a 1.2×10^11 matrix condition number.

Adaptive Hammerstein Predistorter Using the Recursive Prediction Error Method

The digital baseband predistorter is an effective technique to compensate for the nonlinearity of power amplifiers （PAs） with memory effects. However, most available adaptive predistorters based on direct learning architectures suffer from slow convergence speeds. In this paper, the recursive prediction error method is used to construct an adaptive Hammerstein predistorter based on the direct learning architecture, which is used to linearize the Wiener PA model. The effectiveness of the scheme is demonstrated on a digital video broadcasting-terrestrial system. Simulation results show that the predistorter outperforms previous predistorters based on direct learning architectures in terms of convergence speed and linearization. A similar algorithm can be applied to estimate the Wiener PA model, which will achieve high model accuracy.

Low-cost FPGA implementation of 2D digital pre-distorter for concurrent dual-band power amplifier

This paper proposes a low-cost hardware architecture based on concurrent dual-band digital pre-distorter （DPD）. The architecture is implemented on field programmable gate array （FPGA） to compensate for the nonlinearity of the concurrent dual-band power amplifier （PA）. This implementation introduces a novel model complexity reduction technique into system, namely, time-division multiplexing for out-of-band lookup tables （LUTs） sharing. Performances are evaluated with an experimental test setup using a wideband class-F PA. The dual-band signal center frequency separated by 80 MHz. Lower and upper center frequency are located at 2.61 GHz and 2.69 GHz, respectively. This novel DPD implementation maintains excellent performance, but uses hardware resources reduced by 29.17% compared with conventional approaches. The results show that the adjacent channel power ratio （ACPR） is less than -59 dBc and normalized mean square error （NMSE） is around - 62dB for lower sideband （LSB） and - 63dB for upper sideband （USB）.