Design of logic process based low-power 512-bit EEPROM for UHF RFID tag chip

A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.

A Photolithography Process Design for 5 nm Logic Process Flow

With the introduction of EUV lithography,the photolithographic process in 5 nm logic process can be simplified to use mostly single exposure method.In a typical 5 nm logic process,the contact-poly pitch(CPP)is 44-50 nm,the minimum metal pitch(MPP)is around 30-32 nm.And the overlay budget is estimated to be 2.5 nm(on product overlay).Although the optical resolution of a 0.33NA exposure tool(such as ASML NXE3400)can reach below 32 nm pitch,stochastics in the EUV absorption in photoresists has limited its application to smaller pitches.For the CPP mentioned above,one can use 193 nm immersion lithography with Self-Aligned Double Patterning(SADP)technique to provide good image contrast(or CDU,LWR)as well as good overlay,as for the 10 and 7 nm generations.In the BEOL,however,the 30-32 pitch cannot be realized by a single EUV exposure with enough printing defect process window.If this pitch is to be done by 193 nm immersion lithography,more than 6-8 exposures are needed with very complicated overlay result.For EUV,this can be done through self-aligned LELE with both good CD and overlay control.We have done an optimization of the photolithographic process parameters for the typical metal with a self-developed aerial image simulator based on rigorous coupled wave analysis(RCWA)algorithm and the Abbe imaging routine with an EUV absorption model which describes stochastics.We have calibrated our model with wafer exposure data from several photoresists under collaboration with IMEC.As we have presented last year,to accommodate all pitches under a logic design rule,as well as to provide enough CDU for the logic device performance,in DUV lithography,a typical minimum exposure latitude(EL)for the poly and metal layers can be set at,respectively,18%and 13%.In EUV,due to the existence of stochastics,13%EL,which corresponds to an imaging contrast of 40%,seems not enough for the metal trenches,and to obtain an imaging contrast close to 100%,which yields an EL of 31.4%means that we need to relax minimum pitch to above 41 nm(conventional imaging limit for 0.33NA).This is the best imaging contrast a photolithographic process can provide to reduce LWR and stochastics.In EUV,due to the significantly smaller numerical apertures compared to DUV,the aberration impact can cause much more pronounced image registration error,in order to satisfy 2.5 nm total overlay,the aberration induced shift needs to be kept under 0.2 nm.We have also studied shadowing effect and mask 3D scattering effect and our results will be provided for discussion.

Design of 512-bit logic process-based single poly EEPROM IP

A single poly EEPROM cell circuit sharing the deep N-well of a cell array was designed using the logic process. The proposed cell is written by the FN tunneling scheme and the cell size is 41.26 μm2, about 37% smaller than the conventional cell. Also, a small-area and low-power 512-bit EEPROM IP was designed using the proposed cells which was used for a 900 MHz passive UHF RFID tag chip. To secure the operation of the cell proposed with 3.3 V devices and the reliability of the used devices, an EEPROM core circuit and a DC-DC converter were proposed. Simulation results for the designed EEPROM IP based on the 0.18μm logic process show that the power consumptions in read mode, program mode and erase mode are 11.82, 25.15, and 24.08 ~tW, respectively, and the EEPROM size is 0.12 mm2.

Cost of Multicast Logical Key Tree Based on Hierarchical Data Processing

How to design a multicast key management system with high performance is a hot issue now. This paper will apply the idea of hierarchical data processing to construct a common analytic model based on directed logical key tree and supply two important metrics to this problem： re-keying cost and key storage cost. The paper gives the basic theory to the hierarchical data processing and the analyzing model to multieast key management based on logical key tree. It has been proved that the 4-ray tree has the best performance in using these metrics. The key management problem is also investigated based on user probability model, and gives two evaluating parameters to re-keying and key storage cost.

Modeling and Analysis of Data Dependencies in Business Process for Data-Intensive Services

With the growing popularity of data-intensive services on the Internet, the traditional process-centric model for business process meets challenges due to the lack of abilities to describe data semantics and dependencies, resulting in the inflexibility of the design and implement for the processes. This paper proposes a novel data-aware business process model which is able to describe both explicit control flow and implicit data flow. Data model with dependencies which are formulated by Linear-time Temporal Logic(LTL) is presented, and their satisfiability is validated by an automaton-based model checking algorithm. Data dependencies are fully considered in modeling phase, which helps to improve the efficiency and reliability of programming during developing phase. Finally, a prototype system based on j BPM for data-aware workflow is designed using such model, and has been deployed to Beijing Kingfore heating management system to validate the flexibility, efficacy and convenience of our approach for massive coding and large-scale system management in reality.

一种Colored WF_logic Net的工作流过程建模

结合着色Petri网和WL_net相关理论,提出有色工作流逻辑网(CWL_net)这一概念来实现工作流的过程建模。最后以保险索赔业务过程为例,采用绘制可达树的方法分析了业务流程的合理性。利用CWL_net可以准确描述业务流程的工作流逻辑,且这种逻辑结构可以区分工作流具体流程中不同变迁产生的任务完成信息,避免了某些问题。

Formal Reduction of Interfaces to Large-scale Process Control Systems

A formal methodology is proposed to reduce the amount of information displayed to remote human operators at interfaces to large-scale process control plants of a certain type. The reduction proceeds in two stages. In the first stage, minimal reduced subsets of components, which give full information about the state of the whole system, are generated by determining functional dependencies between components. This is achieved by using a temporal logic proof obligation to check whether the state of all components can be inferred from the state of components in a subset in specified situations that the human operator needs to detect, with respect to a finite state machine model of the system and other human operator behavior. Generation of reduced subsets is automated with the help of a temporal logic model checker. The second stage determines the interconnections between components to be displayed in the reduced system so that the natural overall graphical structure of the system is maintained. A formal definition of an aesthetic for the required subgraph of a graph representation of the full system, containing the reduced subset of components, is given for this purpose. The methodology is demonstrated by a case study.

A consistency improving method in the analytic hierarchy process based on directed circuit analysis

Test of consistency is critical for the analytic hierarchy process(AHP) methodology. When a pairwise comparison matrix(PCM) fails the consistency test, the decision maker(DM) needs to make revisions. The state of the art focuses on changing a single entry or creating a new matrix based on the original inconsistent matrix so that the modified matrix can satisfy the consistency requirement. However, we have noticed that the reason that causes inconsistency is not only numerical inconsistency, but also logical inconsistency, which may play a more important role in the whole inconsistency. Therefore, to realize satisfactory consistency, first of all, we should change some entries that form a directed circuit to make the matrix logically consistent, and then adjust other entries within acceptable deviations to make the matrix numerically consistent while preserving most of the original comparison information. In this paper, we firstly present some definitions and theories, based on which two effective methods are provided to identify directed circuits. Four optimization models are proposed to adjust the original inconsistent matrix. Finally, illustrative examples and comparison studies show the effectiveness and feasibility of our method.

面向学科交叉融合的综合性实训教学装置设计与教学实践

针对工程训练实训教学装置功能单一、缺乏多学科交叉与整合能力等问题,以多种特征的物料识别与分拣为应用背景,在综合应用PLC控制技术、传感器技术、气动控制与机电传动控制技术的基础上,结合数字图像处理与卷积神经网络技术,基于树莓派与Jetson嵌入式计算平台,自主研制了一种物料特征识别与分拣综合实训教学装置。与现有同类实训装置相比,该自制实训装置具有体积小,功能多和成本低的优势。实践教学表明,将传统PLC控制与人工智能技术元素有机结合,以及将课内教学延伸至创客活动和学生第二课堂,能有效提升学生的工程认知水平和工程实践能力,体现多学科交叉、多技术融合的高等工程教育特征。

全过程人民民主的时代逻辑、制度体系与发展向度

发展全过程人民民主是遵循社会主义民主政治建设规律,推进中国式现代化的本质要求。全过程人民民主在理论内涵上,将过程与形式、结果与绩效等融合起来,将人民民主与国家意志相统一,丰富了马克思主义民主理论;在具体实践中,全过程人民民主依托于中国特色社会主义制度体系,包括党的领导制度、人民代表大会制度、协商民主制度、基层民主制度等具体制度安排,以程序化、规范化和制度化为基本要求,是全链条、全方位、全覆盖的民主。在发展向度上,主要有四个着力点:一是加强民主制度建设,进一步提高民主政治的成熟度和稳定性;二是推进民主法治建设,进一步保障人民群众的合法权益;三是深化协商民主实践,进一步提高协商民主的广泛性和实效性;四是加强技术赋能创新,提升民主参与效能,为全过程人民民主的发展提供有力支撑。

ANALYSIS AND DESIGN OF A NEURAL CHIP USED FOR BINARY IMAGE PROCESSING

Based on the model of a formal neuron proposed by McCulloch and Pitts,a kind ofneural circuit,which is a CMOS Variable Threshold Logic(VTL)circuit,is given in this paperconsidering the features of the binary image processing system.The theoretical analysis,andthe simulations for the building block circuits such as D/A converters,comparator and so on aregiven.The layout design of the whole circuit are also given.The binary image processing can berealized by using the VTL circuit combined with its external auxiliary circuits.

2D PHASE SHIFTING AND LOGICAL MOIRE USED IN FRINGES ANALYSIS

Phase Shifting And Logical Moire (PSALM) is a kind of computer image processing method which can be used in phase measurement and to obtain the shape, deformation and strain distribution of an object.This paper presents the structure and working procedure of a 2D phase measurement PSALM2D program and its application. When analyzing moire interferometric fringes,we can obtain 2D distribution of displacement and strain.When it is used in reflection moire we can measure the slope of a specimen.Satisfactory visualization and quantitative results are given by PSALM2D.

中华人民共和国成立75年来大学生思想政治教育发展的历程、逻辑与展望

中国共产党历来高度重视大学生思想政治教育工作。作为国家意识形态建设的重要组成部分,大学生思想政治教育以其鲜明的政治性,与党和国家的发展密切相连,并呈现出不同的阶段性特征。系统梳理中华人民共和国成立75年以来大学生思想政治教育经历的起步探索期、曲折前行期、科学发展期和创新发展期等历程,深入把握其在育人目标、育人内容、育人载体和育人格局的逻辑变迁,深化大学生思想政治教育发展的规律性认识,着力探寻新时代大学生思想政治教育建设发展的未来路径,以期推动新时代大学生思想政治教育工作的创新发展。

Evaluation of Selected Control Programming Languages for Process Engineers by Means of Cognitive Effectiveness and Dimensions

Different programming languages can be used for discrete, abstract and process-oriented programming. Depending on the application, there exist additional requirements, which are not fulfilled by every programming language. Flexible programming and maintainability are especially important requirements for process engineers. In this paper, the programming languages Activity Diagram, State Chart Diagram and Sequential Function Chart are compared and evaluated with regard to these requirements. This evaluation is based on the principles of cognitive effectiveness and cognitive dimensions. The aim of this paper is to identify the programming language suited best for controlling sequential processes, e.g. thermomechanical or batch processes.

新中国成立75年来劳动教育的演进历程、发展逻辑与基本经验

新中国成立75年来,劳动教育按照党的教育方针,从无到有,由弱到强,历经酝酿探索、改革发展、体系深化、全面育人四个发展阶段,取得巨大成就。在发展过程中,我国劳动教育形成了根植于中国化、时代化的马克思主义劳动教育观发展、劳动的多样性决定劳动教育全面性发展、劳动教育从外在设计到内生动力双重发展、创造性劳动教育推进新质生产力发展四重逻辑,凝练出始终坚持党的领导把握育人方向、与时俱进构建劳动教育与生产劳动社会实践相融合的体制机制、分级分类分域有针对性构建劳动教育体系、不断加强劳动价值观和劳动精神的养成教育四条基本经验。

两岸融合发展示范区建设的逻辑理路和实践进路——基于“结构-过程”框架的分析

建设两岸融合发展示范区,是推进两岸关系和平发展和服务祖国统一大业的重大战略安排。基于结构功能主义理论,应用“结构-过程”框架,建构两岸融合发展示范区研究模型。从结构角度分析,可以清晰展现两岸融合发展示范区在内涵、空间两个维度的全领域、全区域的全域网格化图景;从过程角度分析,可以动态体现两岸融合发展中两类主体、两种不同方向作用力的互动作用过程。两岸融合发展示范区建设蕴含了社会系统建构的内在逻辑机理,是两岸关系领域理论与实践相结合的创新探索。两岸融合发展示范区是一项创新性系统工程,在结构层面要强化系统观念,完善两岸融合发展示范区有机系统;在过程层面要强化合作观念,推动两岸融合发展示范区合作共建;在创新层面要强化质效观念,实现两岸融合发展示范区建设规划目标。

Multiyear Discrete Stochastic Programming with a Fuzzy Semi-Markov Process

Drought conditions at a given location evolve randomly through time and are typically characterized by severity and duration. Researchers interested in modeling the economic effects of drought on agriculture or other water users often capture the stochastic nature of drought and its conditions via multiyear, stochastic economic models. Three major sources of uncertainty in application of a multiyear discrete stochastic model to evaluate user preparedness and response to drought are: (1) the assumption of independence of yearly weather conditions, (2) linguistic vagueness in the definition of drought itself, and (3) the duration of drought. One means of addressing these uncertainties is to re-cast drought as a stochastic, multiyear process using a “fuzzy” semi-Markov process. In this paper, we review “crisp” versus “fuzzy” representations of drought and show how fuzzy semi-Markov processes can aid researchers in developing more robust multiyear, discrete stochastic models.

Voice Control for an Industrial Robot as a Combination of Various Robotic Assembly Process Models

Models for the design of assembly processes are considered. Various models for the voice control of an industrial robot are considered: a logical model, semantic networks, a frame model and Petri nets. It is shown that this set of models allows describing the process of designing the technological process for an industrial robot. The logical model of the technological process allows you to define logical relationships. A model based on semantic networks describes the relationship between assembly units in a detail. This allows you to determine the order and method of registration, as well as the mutual orientation of assembly units in the product. The frame model provides the ability to streamline the execution of the build process. A model based on Petri nets allows one to describe the type and sequence of technological transitions. Based on the proposed models, a method of voice control for an industrial robot is developed. The basic principles of voice control for an industrial robot are considered.

PRODUCT MODELING AND PROCESS PLANNING WITHIN CONCURRENT ENGINEERING ENVIRONMENT

A prodouct modeling and a process planning that are two essential basses of realizing concurrent engineering are investigated , a logical modeling technique , grammar representation scheme of technology knowledge and architecture of expert system for process planning within con- current engineering environment are proposed. They have been utilized in a real reaserch project.

建构主义视域下全球体育治理制度建构的过程逻辑研究

从建构主义视角提出全球体育治理制度建构的过程分析框架。研究发现:在全球体育治理制度建构过程中,领导型制度倡议者理念偏差、观念性共识凝聚梗阻、战略竞争思维主导国际体育制度改革、制度霸权干扰观念制度化进程是造成体育制度供给失衡、体育制度黏性、制度非中性和制度碎片化等制度建构结果不理想的根源。从制度建构过程中溯源制度建构负向结果的成因——观念障碍,提出全球体育治理制度优化的可行路径。