A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are...A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate （MCP） stack, and a wedge and strip anode （WSA）. The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.展开更多
A novel concept of collision avoidance single-photon light detection and ranging（LIDAR） for vehicles has been demonstrated, in which chaotic pulse position modulation is applied on the transmitted laser pulses for r...A novel concept of collision avoidance single-photon light detection and ranging（LIDAR） for vehicles has been demonstrated, in which chaotic pulse position modulation is applied on the transmitted laser pulses for robust anti-crosstalk purposes. Besides, single-photon detectors（SPD） and time correlated single photon counting techniques are adapted, to sense the ultra-low power used for the consideration of compact structure and eye safety. Parameters including pulse rate, discrimination threshold, and number of accumulated pulses have been thoroughly analyzed based on the detection requirements, resulting in specified receiver operating characteristics curves. Both simulation and indoor experiments were performed to verify the excellent anti-crosstalk capability of the presented collision avoidance LIDAR despite ultra-low transmitting power.展开更多
The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from volta...The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.展开更多
基金Supported by the National Natural Science Foundation of China under Grant No 11375179
文摘A novel FPGA-based pulse pile-up rejection method for single photon imaging detectors is reported. Tile method is easy to implement in FPGAs for real-time data processing. The rejection principle and entire design are introduced in detail. The photon counting imaging detector comprises a micro-channel plate （MCP） stack, and a wedge and strip anode （WSA）. The resolution mask pattern in front of the MCP can be reconstructed after data processing in the FPGA. For high count rates, the rejection design can effectively reduce the impact of the pulse pile-up on the image. The resolution can reach up to 140μm. The pulse pile-up rejection design can also be applied to high-energy physics and particle detection.
基金Project supported by Tsinghua University Initiative Scientific Research Program,China(Grant No.2014z21035)
文摘A novel concept of collision avoidance single-photon light detection and ranging（LIDAR） for vehicles has been demonstrated, in which chaotic pulse position modulation is applied on the transmitted laser pulses for robust anti-crosstalk purposes. Besides, single-photon detectors（SPD） and time correlated single photon counting techniques are adapted, to sense the ultra-low power used for the consideration of compact structure and eye safety. Parameters including pulse rate, discrimination threshold, and number of accumulated pulses have been thoroughly analyzed based on the detection requirements, resulting in specified receiver operating characteristics curves. Both simulation and indoor experiments were performed to verify the excellent anti-crosstalk capability of the presented collision avoidance LIDAR despite ultra-low transmitting power.
文摘The design and implementation of a novel ADC architecture called ring-ADC for digital voltage regulator module controllers are presented. Based on the principle of voltage-controlled oscillators＇ transform from voltage to frequency,the A/D conversion of ring-ADC achieves good linearity and precise calibration against process variations compared with the delay-line ADC. A differential pulse counting discriminator also helps decrease the power consumption of the ring-ADC. It is fabricated with a Chartered 0.35μm CMOS process, and the measurement results of the integral and differential nonlinearity performance are 0.92LSB and 1.2LSB respectively. The maximum gain error measured in ten sample chips is ± 3.85%. With sampling rate of 500kHz and when the voltage regulator module （VRM） works in steady state, the ring-ADC＇s average power consumption is 2.56mW. The ring-ADC is verified to meet the requirements for digital VRM controller application.
