Low-power, high-speed, and area-efficient sequential circuits by quantum-dot cellular automata: T-latch and counter study

Quantum-dot cellular automata(QCA)is a new nanotechnology for the implementation of nano-sized digital circuits.This nanotechnology is remarkable in terms of speed,area,and power consumption compared to complementary metal-oxide-semiconductor(CMOS)technology and can significantly improve the design of various logic circuits.We propose a new method for implementing a T-latch in QCA technology in this paper.The proposed method uses the intrinsic features of QCA in timing and clock phases,and therefore,the proposed cell structure is less occupied and less power-consuming than existing implementation methods.In the proposed T-latch,compared to previous best designs,reductions of 6.45%in area occupation and 44.49%in power consumption were achieved.In addition,for the first time,a reset-based T-latch and a T-latch with set and reset capabilities are designed.Using the proposed T-latch,a new 3-bit counter is developed which reduces 2.14%cell numbers compared to the best of previous designs.Moreover,based on the 3-bit counter,a 4-bit counter is designed,which reduces 0.51%cell numbers and 4.16%cross-section area compared to previous designs.In addition,two selective counters are introduced to count from 0 to 5 and from 2 to 5.Simulations were performed using QCADesigner and QCAPro tools in coherence vector engine mode.The proposed circuits are compared with related designs in terms of delay,cell numbers,area,and leakage power.