Optical Packet Switching (OPS) and transmission networks based on Wavelength Division Multiplexing (WDM) have been increasingly deployed in the Internet infrastructure over the last decade in order to meet the huge in...Optical Packet Switching (OPS) and transmission networks based on Wavelength Division Multiplexing (WDM) have been increasingly deployed in the Internet infrastructure over the last decade in order to meet the huge increasing demand for bandwidth. Several different technologies have been developed for optical packet switching such as space switches, broadcast-and-select, input buffered switches and output buffered switches. These architectures vary based on several parameters such as the way of optical buffering, the placement of optical buffers, the way of solving the external blocking inherited from switching technologies in general and the components used to implement the WDM. This study surveys most of the exiting optical packet switching architectures. A simulation-based comparison of input buffered and output buffered architectures is presented. The performance analysis of the selected two architectures is derived using simulation program and compared at different scenarios. We found that the output buffered architectures give better performance than input buffered architectures. The simulation results show that the-broadcast-and-select architecture is attractive in terms that it has lees number of components compared to other switches.展开更多
Resistive Random Access Memory(ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance.However,design of these accelerators faces a num...Resistive Random Access Memory(ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance.However,design of these accelerators faces a number of challenges including imperfections of the Re RAM device and a large amount of calculations required to accurately simulate the former.We present XB-SIM,a simulation framework for Re RAM-crossbar-based Convolutional Neural Network(CNN)accelerators.XB-SIM can be flexibly configured to simulate the accelerator’s structure and clock-driven behaviors at the architecture level.This framework also includes an Re RAM-aware Neural Network(NN)training algorithm and a CNN-oriented mapper to train an NN and map it onto the simulated design efficiently.Behavior of the simulator has been verified by the corresponding circuit simulation of a real chip.Furthermore,a batch processing mode of the massive calculations that are required to mimic the behavior of Re RAM-crossbar circuits is proposed to fully apply the computational concurrency of the mapping strategy.On CPU/GPGPU,this batch processing mode can improve the simulation speed by up to 5.02 or 34.29.Within this framework,comprehensive architectural exploration and end-to-end evaluation have been achieved,which provide some insights for systemic optimization.展开更多
文摘Optical Packet Switching (OPS) and transmission networks based on Wavelength Division Multiplexing (WDM) have been increasingly deployed in the Internet infrastructure over the last decade in order to meet the huge increasing demand for bandwidth. Several different technologies have been developed for optical packet switching such as space switches, broadcast-and-select, input buffered switches and output buffered switches. These architectures vary based on several parameters such as the way of optical buffering, the placement of optical buffers, the way of solving the external blocking inherited from switching technologies in general and the components used to implement the WDM. This study surveys most of the exiting optical packet switching architectures. A simulation-based comparison of input buffered and output buffered architectures is presented. The performance analysis of the selected two architectures is derived using simulation program and compared at different scenarios. We found that the output buffered architectures give better performance than input buffered architectures. The simulation results show that the-broadcast-and-select architecture is attractive in terms that it has lees number of components compared to other switches.
基金supported in part by Beijing Academy of Artificial Intelligence(BAAI)(No.BAAI2019ZD0403)Beijing Innovation Center for Future Chip,Tsinghua Universitythe Science and Technology Innovation Special Zone Project,China。
文摘Resistive Random Access Memory(ReRAM)-based neural network accelerators have potential to surpass their digital counterparts in computational efficiency and performance.However,design of these accelerators faces a number of challenges including imperfections of the Re RAM device and a large amount of calculations required to accurately simulate the former.We present XB-SIM,a simulation framework for Re RAM-crossbar-based Convolutional Neural Network(CNN)accelerators.XB-SIM can be flexibly configured to simulate the accelerator’s structure and clock-driven behaviors at the architecture level.This framework also includes an Re RAM-aware Neural Network(NN)training algorithm and a CNN-oriented mapper to train an NN and map it onto the simulated design efficiently.Behavior of the simulator has been verified by the corresponding circuit simulation of a real chip.Furthermore,a batch processing mode of the massive calculations that are required to mimic the behavior of Re RAM-crossbar circuits is proposed to fully apply the computational concurrency of the mapping strategy.On CPU/GPGPU,this batch processing mode can improve the simulation speed by up to 5.02 or 34.29.Within this framework,comprehensive architectural exploration and end-to-end evaluation have been achieved,which provide some insights for systemic optimization.
