OPTIMIZATION DESIGN METHOD FOR INPUT IMPEDANCE MATCHING NETWORK OF LOW NOISE AMPLIFIER

According to the theories of optimal noise match and optimal power match, a method for calculating the optimal source impedance of low noise amplifier （LNA） is proposed based on the input reflection coefficient S11. Moreover.with the help of Smith chart, the calculation process is detailed, and the trade-off between the lowest noise figure and the maximum power gain is obtained during the design of LNA input impedance matching network. Based on the Chart 0. 35-μm CMOS process, a traditional cascode LNA circuit is designed and manufactured. Simulation and experimental results have a good agreement with the theoretical analysis, thus proving the correctness of theoretical analysis and the feasibility of the method.

Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

Low-Noise Amplification, Detection and Spectroscopy of Ultra-Cold Systems in RF Cavities

The design and development of a cryogenic Ultra-Low-Noise Signal Amplification (ULNA) and detection system for spectroscopy of ultra-cold systems are reported here for the operation in the 0.5 - 4 GHz spectrum of frequencies (the “L” and “S” microwave bands). The design is suitable for weak RF signal detection and spectroscopy from ultra-cold systems confined in cryogenic RF cavities, as entailed in a number of physics, physical chemistry and analytical chemistry applications, such as NMR/NQR/EPR and microwave spectroscopy, Paul traps, Bose-Einstein Condensates (BEC’s) and cavity Quantum Electrodynamics (cQED). Using a generic Low-Noise Amplifier (LNA) architecture for a GaAs enhancement mode High-Electron Mobility FET device, our design has especially been devised for scientific applications where ultra-low-noise amplification systems are sought to amplify and detect weak RF signals under various conditions and environments, including cryogenic temperatures, with the least possible noise susceptibility. The amplifier offers a 16 dB gain and a 0.8 dB noise figure at 2.5 GHz, while operating at room temperature, which can improve significantly at low temperatures. Both dc and RF outputs are provided by the amplifier to integrate it in a closed-loop or continuous-wave spectroscopy system or connect it to a variety of instruments, a factor which is lacking in commercial LNA devices. Following the amplification stage, the RF signal detection is carried out with the help of a post-amplifier and detection system based upon a set of Zero-Bias Schottky Barrier Diodes (ZBD’s) and a high-precision ultra-low noise jFET operational amplifier. The scheme offers unique benefits of sensitive detection and very-low noise amplification for measuring extremely weak on-resonance signals with substantial low- noise response and excellent stability while eliminating complicated and expensive heterodyne schemes. The LNA stage is fully capable to be a part of low-temperature experiments while being operated in cryogenic conditions down to about 500 mK.

Radio Frequency Low Noise Amplifier with Linearizing Bias Circuit

A 1.34 GHz-1=60 MHz low noise amplifier （LNA） designed in a 0.35 pm SiGe process is presented. The designed LNA exhibits a power gain of 21.46 dB and a noise figure （NF） of 1.27 dB at 1.34 GHz. The linearity is improved with an active biasing technique. The post-layout simulation shows an input referred 1-dB compression point （IPldn） of-11.52 dBm. Compared with the recent reported high gain LNAs, the proposed LNA has a much better linearity without degrading other performance. The LNA draws 10 mA current from a 3.3 V power supply.

Implementation of a 6 GHz band TDD RF transceiver for the next generation mobile communication system

The development of a high performance wideband radio frequency （RF） transceiver used in the next generation mobile communication system is presented. The developed RF transceiver operates in the 6 to 6.3 GHz band and the channel bandwidth is up to 100 MHz. It operates in the time division duplex （TDD） mode and supports the multiple-input multipleoutput （MIMO） technique for the international mobile telecommunications （IMT）-advanced systems. The classical superheterodyne scheme is employed to achieve optimal performance. Design issues of the essential components such as low noise amplifier, power amplifier and local oscillators are described in detail. Measurement results show that the maximum linear output power of the RF transceiver is above 23 dBm, and the gain and noise figure of the low noise amplifier is around 24 dB and below 1 dB, respectively. Furthermore, the error vector magnitude （EVM） measurement shows that the performance of the developed RF transceiver is well beyond the requirements of the long term evolution （LTE）-advanced system. With up to 8 x 8 MIMO configuration, the RF transceiver supports more than a 1 Gbit/s data rate in field tests.

RF-MEMS滤波器的高性能接口电路设计

提出了一种适用于射频—微机电系统(RF-MEMS)滤波器的高性能接口放大电路。利用微纳工艺制备了相对带宽为1.4%、中心频率为73.02 MHz的硅基MEMS滤波器,针对其高阻抗、高插入损耗特性,设计了基于运算放大器的低噪声、高增益的两级放大电路和阻抗匹配电路。仿真结果表明:接口电路对高频的MEMS滤波器微弱电流信号具有良好的放大效果,增益可达62.75d B,噪声系数为3.35d B,S22反射系数为-46.91 d B,使RF-MEMS滤波器的插入损耗降低至0.56 d B。测试与PCB板级电路级联的MEMS滤波器输出信号表明:RF-MEMS滤波器的插入损耗降至16.2d B,相对带宽为1.4%,中心频率为73.02 MHz,提升了MEMS滤波器在无线通信中的应用潜力。

UHF RFID阅读器中的堆叠式CMOS LNA设计

提出了一种基于0.25μm标准CMOS工艺,可用于UHF RFID(超高频射频识别)阅读器前端的低噪声放大器。根据低噪声放大器的匹配、噪声和增益分析,结合射频识别系统的理论计算,提出堆叠器件的电路结构达到电流复用,以降低功耗并保证增益。测试结果表明,在2.5 V供电时,放大器可以提供约26.3 dB的前向增益,噪声系数约为1.9 dB,放大电路从电源电压上抽取5.8 mA左右的工作电流,反向隔离度达到-40 dB,放大器的IIP3约为-15 dBm。

RFID低噪声放大器设计与仿真

研究低噪声放大器和优化问题,射频识别系统读卡器的读卡性能,决定了放大器的优化效果。为提高系统性能,采用参数方程和ADS(Advanced Design System)内部函数相结合的方法,通过对恒增益圆、恒噪声系数圆来设计低噪声放大器。方法将"波"的概念引入放大器的设计过程中,将放大器的稳定性、增益、噪声和阻抗匹配等性能参数用波的概念来表述。仿真结果表明,设计完全满足性能指标要求,使基于S参数的小信号放大器的分析与设计变得非常方便。证明方法为实际低噪声放大器优化设计提供参考。

无线系统中的RF器件与电路

介绍了下一代无线系统中存在的问题 ,分别概述了无线系统中 RF器件与电路的发展与现状。

A 0.18μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

A 2.4-GHz low power dual gain low noise amplifier for ZigBee

This paper presents a fully differential dual gain low noise amplifier（DGLNA） for low power 2.45-GHz ZigBee/IEEE 802.15.4 applications.The effect of input parasitics on the inductively degenerated cascode LNA is analyzed.Circuit design details within the guidelines of the analysis are presented.The chip was implemented in SMIC 0.18-μm 1P6M RF/mixed signal CMOS process.The DGLNA achieves a maximum gain of 8 dB and a minimum gain of 1 dB with good input return loss.In high gain mode, the measured noise figure（NF） is 2.3-3 dB in the whole 2.45-GHz ISM band.The measured 1-dB compression point, IIP3 and IIP2 is-9, 1 and 33 dBm, respectively.The DGLNA consumes 2 mA of current from a 1.8 V power supply.

ESD-Induced Noise to Low Noise Amplifier Circuits in BiCMOS

Electrostatic discharge （ESD） induced parasitic effects have serious impacts on performance of radio frequency （RF） integrated circuits （IC）. This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures （NFs） of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier （LNA） circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.

A NOVEL SIMULTANEOUS NOISE AND INPUT VSWR MATCHING TECHNIQUE FOR BROADBAND LNA

The Simultaneous Noise and Input Voltage Standing Wave Ratio (VSWR) Matching (SNIM) condition for Low Noise Amplifier (LNA), in principle, can only be satisfied at a single fre-quency. In this paper, by analyzing the fundamental limitations of the narrowband SNIM technique for the broadband application, the authors present a broadband SNIM LNA systematic design technique. The designed LNA guided by the proposed methodology achieves 10 dB power gain with a low Noise Figure of 0.53 dB. Meanwhile, it provides wonderful input matching of 27 dB across the fre-quency range of 3～5 GHz. Therefore, broadband SNIM is realized.

Design of a low-power 433/915-MHz RF front-end with a current-reuse common-gate LNA

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier （LNA）, current-reuse V-I converter, active double balanced mixer and transimpedance amplifier for short range device （SRD） applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18μm RFCMOS process and occupies a silicon area of just 0.11 mm^2. Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of -24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption.

CMOS Dual-Band Low Noise Amplifer

A CMOS dual-band low noise amplifer (LNA) design is presented.The purpose of th is work is intended to substitute only one LNA for two individual LNA's in dual -band transceivers for applications such as wireless local area network complying with both IEEE 802.11a and 802.11b/g.Dua l-band simultaneous input power and noise matching and load shaping are discuss ed.The chip is implemented in 0.25μm CMOS mixed and RF process.The measured pe rformance is summarized and discussed.

A 31.7-GHz high linearity millimeter-wave CMOS LNA using an ultra-wideband input matching technique

A CMOS low-noise amplifier （LNA） operating at 31.7 GHz with a low input return loss （S11） and high linearity is proposed. The wideband input matching was achieved by employing a simple LC compounded network to generate more than one S11 dip below -10 dB level. The principle of the matching circuit is analyzed and the critical factors with significant effect on the input impedance （Zin） are determined. The relationship between the input impedance and the load configuration is explored in depth, which is seldom concentrated upon previously. In addition, the noise of the input stage is modeled using a cascading matrix instead of conventional noise theory. In this way Zin and the noise figure can be calculated using one uniform formula. The linearity analysis is also performed in this paper. Finally, an LNA was designed for demonstration purposes. The measurement results show that the proposed LNA achieves a maximum power gain of 9.7 dB and an input return loss of 〈 -10 dB from 29 GHz to an elevated frequency limited by the measuring range. The measured input-referred compression point and the third order inter-modulation point are -7.8 and 5.8 dBm, respectively. The LNA is fabricated in a 90-nm RF CMOS process and occupies an area of 755 × 670μm2 including pads. The whole circuit dissipates a DC power of 24 mW from one 1.3-V supply.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

An inductorless multi-mode RF front end for a global navigation satellite system （GNSS） receiver is presented. Unlike the traditional topology of a low noise amplifier （LNA）, the inductorless current-mode noise- canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier （RFA） further am- plifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down- converts the signals to the intermediate frequency （IF） band and conveys the signals to the analogue blocks. The local oscillator （LO） buffer divides the output frequency of the voltage controlled oscillator （VCO） and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220×280 μm2.

基于巡检无人机增程装置的设计和实现

目前燃气管线、电力巡检无人机系统的需求具有多样性,为适应巡检无人机不同距离的遥控、遥测、遥感等信息的传输,设计了一种基于巡检无人机测控系统的增程装置。该装置在高速射频开关自动切换架构技术基础上,采用高集成度的模块化、轻小型化设计。可实现巡检无人机不同测控距离、不同频段的设计应用,为巡检类无人机提供有效且多样的测控方案。

一个2.4 GHz集成的SP3T射频开关和低噪声放大器

基于90 nm SOI CMOS工艺实现的应用于无线局域网的2.4 GHz集成的单刀三掷(SP3T)射频开关和低噪声放大器.射频开关采用了一种低功耗的等效负压偏置方法,该方法能够在不使用负电压的前提下使关断状态晶体管获得等效的负压偏置,从而提高射频开关的线性度.低噪声放大器采用了负反馈技术和导数叠加技术提高线性度,利用导数叠加技术减小低噪声放大器的三阶非线性,进一步提高了负反馈低噪声放大器的线性度.低噪声放大器与射频开关集成,并带有Bypass衰减通路.测试结果表明,射频开关的发射支路实现了0.95 dB的插入损耗和34 dBm的输入1 dB压缩点,蓝牙支路具有1.68 dB的插入损耗和30 dBm的输入1 dB压缩点.在2 V供电下,接收支路在高增益模式下具有15.8 dB的增益,1.7 dB的噪声系数和7.6 dBm的输入三阶交调点,功耗28.6 mW,在Bypass模式下具有7.2 dB的插入损耗和22 dBm的输入三阶交调点.

噪声系数最小1.6 dB有高带外抑制的5~6 GHz射频接收前端芯片

为了满足射频通信前端接收部分对高线性与带外信号抑制能力的要求,基于130 nm绝缘体上硅工艺设计并实现工作在5~6 GHz的射频接收前端芯片.该前端芯片由带有旁路和带外抑制功能的低噪声放大器(LNA)、射频开关和带隙基准偏置电路等组成.基于共源共栅结构的LNA,在输入匹配中使用LC陷波实现带外抑制;在偏置电路中,使用带隙基准电流源对LNA的偏置进行温度补偿,屏蔽电源纹波影响.对该前端芯片进行流片加工并测试,结果表明,当工作频率为5~6 GHz时,芯片的接收增益为13.4~14.0 dB,输入与输出反射系数均小于-10 dB,频带内的最小噪声系数为1.6 dB,在工作频率内1 dB压缩点的输入功率大于-4 dBm,输入三阶交调点大于+7 dBm.低噪声放大器在整个工作频段内无条件稳定,在2 V供电电压下电路的直流功耗为30 mW,芯片面积为0.56 mm2.