A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional G...A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.展开更多
A low-sidelobe circularly-polarized(CP) microstrip patch array for 2.4 GHz radio frequency identification(RFID) readers is presented.The antenna array with a Chebyshev current distribution is composed of 6 microstrip ...A low-sidelobe circularly-polarized(CP) microstrip patch array for 2.4 GHz radio frequency identification(RFID) readers is presented.The antenna array with a Chebyshev current distribution is composed of 6 microstrip elements.The CP operation is obtained by the quasi-square patch with difference in lengths of the two sides.The antenna has been investigated numerically and experimentally.Measured results show that the array has a Chebyshev pattern with the sidelobe level of-23 dB, the half-power beamwidth of 16° and an impedance bandwidth(S11≤-10 dB) of 130 MHz, which is suitable for RFID reader applications.展开更多
To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as...To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.展开更多
A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a ...A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.展开更多
文摘A quadrature mixer with a shared transconductor stage is analyzed,including voltage conversion gain, linearity, noise figure, and image rejection. The analysis indicates it has better performance than a conventional Gilbert mixer pair in commutating mode. A quadrature down-conversion mixer based on this topology is designed and optimized for an ultra high frequency RFID reader. Operating in the 915MHz ISM band, the presented quadrature mixer measures a conversion gain of 12.5dB,an IIP3 of 10dBm, an IIP2 of 58dBm, and an SSB noise figure of 17.6riB. The chip was fabricated in a 0. 18μm 1P6M RF CMOS process and consumes only 3mA of current from a 1.8V power supply.
基金supported by the Shanghai Leading Academic Discipline Project (Grant No.T0102)
文摘A low-sidelobe circularly-polarized(CP) microstrip patch array for 2.4 GHz radio frequency identification(RFID) readers is presented.The antenna array with a Chebyshev current distribution is composed of 6 microstrip elements.The CP operation is obtained by the quasi-square patch with difference in lengths of the two sides.The antenna has been investigated numerically and experimentally.Measured results show that the array has a Chebyshev pattern with the sidelobe level of-23 dB, the half-power beamwidth of 16° and an impedance bandwidth(S11≤-10 dB) of 130 MHz, which is suitable for RFID reader applications.
文摘To implement a fully-integrated on-chip CMOS power amplifier（PA） for RFID readers,the resonant frequency of each matching network is derived in detail.The highlight of the design is the adoption of a bonding wire as the output-stage inductor.Compared with the on-chip inductors in a CMOS process,the merit of the bondwire inductor is its high quality factor,leading to a higher output power and efficiency.The disadvantage of the bondwire inductor is that it is hard to control.A highly integrated class-E PA is implemented with 0.18-μm CMOS process.It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm.The maximum power-added efficiency（PAE） is 32.1%.Also,the spectral performance of the PA is analyzed for the specified RFID protocol.
文摘A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16（2^4）sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10^-6, the testing results show that the phase noises are –120.6 dBc/Hz at 1 MHz and –95.0 dBc/Hz at 100 k Hz. The chip is2.1 mm^2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.
