鉴于射频识别(RFID)标签芯片苛刻的资源要求,为解决差分功耗分析(Differential Power Analysis,DPA)对密码算法实现方面的威胁难题,将新型DPA防护技术threshold与Piccolo密码算法相结合,提出了一种适用于RFID标签芯片应用的安全化密码...鉴于射频识别(RFID)标签芯片苛刻的资源要求,为解决差分功耗分析(Differential Power Analysis,DPA)对密码算法实现方面的威胁难题,将新型DPA防护技术threshold与Piccolo密码算法相结合,提出了一种适用于RFID标签芯片应用的安全化密码算法实现方案.分别基于布尔式重组和改进型穷举搜索的方式实现了面积最优的S盒及其逆的threshold(3,3)分享,提出了基于锁存器方式解决S盒及其逆实现中潜在的毛刺威胁问题,在Chartered 0.18μm工艺和100 kHz RFID运行频率下,将该方案的资源消耗控制在2155个等效门,平均电流约为2.60μA,基于FPGA的DPA攻击安全性分析结果表明该方案适合于低成本RFID标签芯片对密码算法轻型及实现安全的要求.展开更多
基于SMIC 0.35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROM IP核。典型情况下,读电流为40μA,页编程电流为250μA,特别适合RFID(Radio Frequency Identification)标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析...基于SMIC 0.35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROM IP核。典型情况下,读电流为40μA,页编程电流为250μA,特别适合RFID(Radio Frequency Identification)标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析,并给出了相应的实现方法。展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
文摘基于SMIC 0.35μm嵌入式EEPROM工艺实现了一款256byte的超低功耗EEPROM IP核。典型情况下,读电流为40μA,页编程电流为250μA,特别适合RFID(Radio Frequency Identification)标签芯片的应用。针对芯片中各种功耗的来源进行了详细的分析,并给出了相应的实现方法。
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
