In radiation measurement and digital nuclear spectrum systems,traditional nuclear signal processing circuits in nuclear electronics have been gradually replaced by digital algorithm modules with the application of hig...In radiation measurement and digital nuclear spectrum systems,traditional nuclear signal processing circuits in nuclear electronics have been gradually replaced by digital algorithm modules with the application of highperformance programmable hardware logic devices(such as FPGA or DSP).Referring to the digital realization method of inverse RC integral circuit systems,the function of the pole-zero cancellation(PZC)circuit was analyzed,a new modified cascade equivalent model of PZC was established,and the time-domain digital PZC(DPZC)recursive algorithm was derived in detail in this study.Two parameters kIand k_(D)are included in the new algorithm,where kIshould match the exponential decay time constant of the input signal to realize the pole-zero compensation,while the decay time constant of the output signal can be changed with the adjustable parameter k_(D)(which is larger than the decay time constant of the input signal).Based on the new DPZC algorithm module,two trapezoidal(triangular)shaping filters were designed and implemented.The amplitude–frequency characteristics of the output signal of the proposed trapezoidal shaping algorithm and the convolution trapezoidal shaping algorithm were compared,with fixed peaking time.The results show that the trapezoidal shaping algorithm based on DPZC can better suppress high-frequency noise.Finally,based on the Na I(Tl)scintillator(u75 mm×75 mm)detector and^(137)Cs source,the effect of the k_(D)value on the energy resolution of the DPZC trapezoidal(triangular)shaping algorithm was studied.The experimental results show that,with an increase in k_(D),the energy resolution of the system improved and reached the maximum when k_(D)was greater than 10,and the optimal energy resolution of the system was 7.72%.展开更多
A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stabili...A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.展开更多
风机并网逆变器及送电系统的稳定性是大规模海上风力发电系统稳定运行的重要保证。提出一种考虑小干扰稳定的海上风电系统控制器参数优化设计方法。首先,利用谐波线性化原理推导了直驱风机并网逆变器、送端采用不控整流器的高压直流(dio...风机并网逆变器及送电系统的稳定性是大规模海上风力发电系统稳定运行的重要保证。提出一种考虑小干扰稳定的海上风电系统控制器参数优化设计方法。首先,利用谐波线性化原理推导了直驱风机并网逆变器、送端采用不控整流器的高压直流(diode-rectifier based HVDC,DR-HVDC)输电系统的序阻抗模型。然后,分析了风场经DR-HVDC并网互联系统的特点,讨论了稳定判据的适用性。进而,从控制器的角度,确定直驱风机并网逆变器控制系统的控制带宽和阻尼比的取值范围。并在此基础上,从系统的角度,综合考虑互联系统的右半平面零极点和控制参数等对阻抗比值的作用。最后,给出直驱风机并网逆变器的控制系统参数优化设计流程。基于Matlab/Simulink建立海上风电经DR-HVDC直流送出系统的时域仿真模型。仿真结果验证了理论分析的正确性和所提方法的有效性。展开更多
Focusing on the linearity shortcoming on a bipolar low noise amplifier(LNA),a new 6 ~14GHz four stage SiGe HBT LNA is proposed.This amplifier adopts a method of gain allocation on multiple stages to avoid the limitati...Focusing on the linearity shortcoming on a bipolar low noise amplifier(LNA),a new 6 ~14GHz four stage SiGe HBT LNA is proposed.This amplifier adopts a method of gain allocation on multiple stages to avoid the limitation on linearity especially with the addition of negative gain on the third stage.To realize gain flatness,extra zero is introduced to compensate the gain roll-off formed by pole,and local shunt-shunt negative feedback is used to widen the bandwidth as well as optimize circuit' s noise.Simulated results have shown that in 6 ~14GHz,this circuit achieves noise figure(NF) less than 3dB,gain of 17.8dB(+0.2dB),input and output reflection parameters of less than- 10 dB,and the K factor is above 1.15.展开更多
基金supported by the National Natural Science Foundation of China(Nos.11975060,12005026,and 12075038)the Fund of Robot Technology Used for Special Environment Key Laboratory of Sichuan Province(No.19kftk02)。
文摘In radiation measurement and digital nuclear spectrum systems,traditional nuclear signal processing circuits in nuclear electronics have been gradually replaced by digital algorithm modules with the application of highperformance programmable hardware logic devices(such as FPGA or DSP).Referring to the digital realization method of inverse RC integral circuit systems,the function of the pole-zero cancellation(PZC)circuit was analyzed,a new modified cascade equivalent model of PZC was established,and the time-domain digital PZC(DPZC)recursive algorithm was derived in detail in this study.Two parameters kIand k_(D)are included in the new algorithm,where kIshould match the exponential decay time constant of the input signal to realize the pole-zero compensation,while the decay time constant of the output signal can be changed with the adjustable parameter k_(D)(which is larger than the decay time constant of the input signal).Based on the new DPZC algorithm module,two trapezoidal(triangular)shaping filters were designed and implemented.The amplitude–frequency characteristics of the output signal of the proposed trapezoidal shaping algorithm and the convolution trapezoidal shaping algorithm were compared,with fixed peaking time.The results show that the trapezoidal shaping algorithm based on DPZC can better suppress high-frequency noise.Finally,based on the Na I(Tl)scintillator(u75 mm×75 mm)detector and^(137)Cs source,the effect of the k_(D)value on the energy resolution of the DPZC trapezoidal(triangular)shaping algorithm was studied.The experimental results show that,with an increase in k_(D),the energy resolution of the system improved and reached the maximum when k_(D)was greater than 10,and the optimal energy resolution of the system was 7.72%.
文摘A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.
基金Projects (51101042, 51271064) supported by the National Natural Science Foundation of ChinaProject (HIT. NSRIF. 201131) supported by the Fundamental Research Funds for the Central Universities, China+1 种基金Projects (2012T50327, 2011M500653) supported by the China Postdoctoral Science FoundationProject supported by the Postdoctoral Science Foundation of Heilongjiang Province, China
文摘风机并网逆变器及送电系统的稳定性是大规模海上风力发电系统稳定运行的重要保证。提出一种考虑小干扰稳定的海上风电系统控制器参数优化设计方法。首先,利用谐波线性化原理推导了直驱风机并网逆变器、送端采用不控整流器的高压直流(diode-rectifier based HVDC,DR-HVDC)输电系统的序阻抗模型。然后,分析了风场经DR-HVDC并网互联系统的特点,讨论了稳定判据的适用性。进而,从控制器的角度,确定直驱风机并网逆变器控制系统的控制带宽和阻尼比的取值范围。并在此基础上,从系统的角度,综合考虑互联系统的右半平面零极点和控制参数等对阻抗比值的作用。最后,给出直驱风机并网逆变器的控制系统参数优化设计流程。基于Matlab/Simulink建立海上风电经DR-HVDC直流送出系统的时域仿真模型。仿真结果验证了理论分析的正确性和所提方法的有效性。
基金Supported by the National Natural Science Foundation of China(No.61076101,61204092,61306033)
文摘Focusing on the linearity shortcoming on a bipolar low noise amplifier(LNA),a new 6 ~14GHz four stage SiGe HBT LNA is proposed.This amplifier adopts a method of gain allocation on multiple stages to avoid the limitation on linearity especially with the addition of negative gain on the third stage.To realize gain flatness,extra zero is introduced to compensate the gain roll-off formed by pole,and local shunt-shunt negative feedback is used to widen the bandwidth as well as optimize circuit' s noise.Simulated results have shown that in 6 ~14GHz,this circuit achieves noise figure(NF) less than 3dB,gain of 17.8dB(+0.2dB),input and output reflection parameters of less than- 10 dB,and the K factor is above 1.15.
