Simulation and research on a 4T-cell based duplication redundancy SRAM for SEU radiation hardening

A novel 4T-cell based duplication redundancy SRAM is proposed for SEU radiation hardening applications. The memory cell is designed with a 65-nm low leakage process; the operation principle and the SEU radiation hardening mechanism are discussed in detail. The SEE characteristics and failure mechanism are also studied with a 3-D device simulator. The results show that the proposed SRAM structure exhibits high SEU hardening performance with a small cell size.

A Radiation Hardened Power Device——VDMNOSFET

A radiation hardened N channel Si power device——VDMNOSFET (Vertical Double Diffused Metal Nitride Oxide Semiconductor Field Effect Transistor) is fabricated by using a double layer (Si 3N 4 SiO 2) gate dielectric and a self aligned heavily doped shallow P + region.The effects of ionizing radiation and transient high dose rate radiation of the power VDMNOSFET are also presented.Good radiation hardening performance is obtained,compared with the conventional power VDMOSFET.For the specified 200V VDMNOSFET,the threshold voltage shifts is only -0 5V at a Gamma dose of 1Mrad(Si) with +10V gate bias;the transconductance is degraded by 10% at a Gamma dose of 1Mrad(Si);and no burnout failures occur at the transient high dose rate of 1×10 12 rad(Si)/s.It is demonstrated that the ionizing radiation tolerance and burnout susceptibilities of the power MOSFET are improved significantly by using a double layer (Si 3N 4 SiO 2) gate dielectric and a self aligned heavily doped shallow P + region.

A novel double-node-upset-resilient radiation-hardened latch

To effectively tolerate a double-node upset,a novel double-node-upset-resilient radiation-hardened latch is proposed in 22 nm complementary-metal-oxide-semiconductor technology.Using three interlocked single-node-upset-resilient cells,which are identically mainly constructed from three mutually feeding back 2-input C-elements,the latch achieves double-node-upset-resilience.Using smaller transistor sizes,clock-gating technology,and high-speed transmission-path,the cost of the latch is effectively reduced.Simulation results demonstrate the double-node-upset-resilience of the latch and also show that compared with the up-to-date double-node-upset-resilient latches,the proposed latch reduces the transmission delay by 72.54%,the power dissipation by 33.97%,and the delay-power-area product by 78.57%,while the average cost of the silicon area is only increased by 16.45%.

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies

A dual double interlocked storage cell(DICE)interleaving layout static random-access memory(SRAM)is designed and manufactured based on 65 nm bulk complementary metal oxide semiconductor technology.The single event upset(SEU)cross sections of this memory are obtained via heavy ion irradiation with a linear energy transfer(LET)value ranging from 1.7 to 83.4 MeV/(mg/cm^(2)).Experimental results show that the upset threshold(LETth)of a 4 KB block is approximately 6 MeV/(mg/cm^(2)),which is much better than that of a standard unhardened SRAM with an identical technology node.A 1 KB block has a higher LETth of 25 MeV/(mg/cm^(2))owing to the use of the error detection and correction(EDAC)code.For a Ta ion irradiation test with the highest LET value(83.4 MeV/(mg/cm^(2))),the benefit of the EDAC code is reduced significantly because the multi-bit upset proportion in the SEU is increased remarkably.Compared with normal incident ions,the memory exhibits a higher SEU sensitivity in the tilt angle irradiation test.Moreover,the SEU cross section indicates a significant dependence on the data pattern.When comprehensively considering HSPICE simulation results and the sensitive area distributions of the DICE cell,it is shown that the data pattern dependence is primarily associated with the arrangement of sensitive transistor pairs in the layout.Finally,some suggestions are provided to further improve the radiation resistance of the memory.By implementing a particular design at the layout level,the SEU tolerance of the memory is improved significantly at a low area cost.Therefore,the designed 65 nm SRAM is suitable for electronic systems operating in serious radiation environments.

Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes

As integrated circuits scale down in size, a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient（SET） pulse quenching induced by single-event charge sharing collection has been widely studied. In this paper, SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation（STI）. The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells. Three-dimensional（3D） technology computer-aided design simulation（TCAD） results show that this technique can achieve efficient SET mitigation.

The dual role of multiple-transistor charge sharing collection in single-event transients

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.

Design of high performance and radiation hardened SPARC-V8 processor

Design of a highly reliable SPARC-V8 processor for space applications requires consideration singleevent effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose（TID）. In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78 9.78 mm^2, and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements＇ experiments, which show TID resistance to 300 krad（Si）, SEL immunity to greater than 92.5 Me V cm^2/mg, and an SEU error rate of 2.51 10^-4 per day.

A dual redundancy radiation-hardened flip–flop based on a C-element in a 65 nm process

A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop.

A novel radiation hardened by design latch

Due to aggressive technology scaling, radiation-induced soft errors have become a serious reliability concern in VLSI chip design. This paper presents a novel radiation hardened by design latch with high single-eventupset （SEU） immunity. The proposed latch can effectively mitigate SEU by internal dual interlocked scheme. The propagation delay, power dissipation and power delay product of the presented latch are evaluated by detailed SPICE simulations. Compared with previous SEU-hardening solutions such as TMR-Latch, the presented latch is more area efficient, delay and power efficient. Fault injection simulations also demonstrate the robustness of the presented latch even under high energy particle strikes.

Design of a total-dose radiation hardened monolithic CMOS DC-DC boost converter

This paper presents the design and implementation of a monolithic CMOS DC-DC boost converter that is hardened for total dose radiation.In order to improve its radiation tolerant abilities,circuit-level and device-level RHBD（radiation-hardening by design） techniques were employed.Adaptive slope compensation was used to improve the inherent instability.The H-gate MOS transistors,annular gate MOS transistors and guard rings were applied to reduce the impact of total ionizing dose.A boost converter was fabricated by a standard commercial 0.35μm CMOS process.The hardened design converter can work properly in a wide range of total dose radiation environments,with increasing total dose radiation.The efficiency is not as strongly affected by the total dose radiation and so does the leakage performance.

Research on single event transient pulse quenching effect in 90 nm CMOS technology

Since single event transient pulse quenching can reduce the SET(single event transient) pulsewidths effectively,the charge collected by passive device should be maximized in order to minimize the propagated SET.From the perspective of the layout and circuit design,the SET pulsewidths can be greatly inhibited by minimizing the layout spacing and signal propagation delay,which sheds new light on the radiation-hardened ICs(integrated circuits) design.Studies show that the SET pulsewidths of propagation are not in direct proportion to the LET(linear energy transfer) of incident particles,thus the defining of the LET threshold should be noted when SET/SEU(single event upset) occurs for the radiation-hardened design.The capability of anti-radiation meets the demand when LET is high but some soft errors may occur when LET is low.Therefore,radiation experiments should be focused on evaluating the LET that demonstrates the worst response to the circuit.

A novel layout for single event upset mitigation in advanced CMOS SRAM cells

A novel layout has been proposed to reduce the single event upset(SEU) vulnerability of SRAM cells.Extensive 3-D technology computer-aided design(TCAD) simulation analyses show that the proposed layout can recover the upset-state much easier than conventional layout for larger space of PMOS transistors.For the angle incidence,the proposed layout is immune from ion hit in two plans,and is more robust against SEU in other two plans than the conventional one.The ability of anti-SEU is enhanced by at least 33% while the area cost reduced by 47%.Consequently,the layout strategy proposed can gain both reliability and area cost benefit simultaneously.

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism（NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS） and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are：（1） with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.（2） Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style（i.e.spacing between transistors and n-well contact area）.（3） Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology

In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.