RECOGNITION OF STRUCTURAL DIAGRAM OF MACHINE TOOL SPEED CHANGE SYSTEM WITH ANY COMPOSITE RATIO

The speeds of output shaft of a machine tool ni=n1E are expressed by the exponentvalues Ej of series ratio . Based on this expression, the inherert law of differences between expo-nents of driven points from the same drive pair and the same driving point and of correspordingdriving points A method for finding out the exponents of the range ratio hat been given accordingto the law and it is called coordinate diagram method. Finally, a mathematical model is constiuctedand a computer programme is designed.

Multiple model particle flter track-before-detect for range ambiguous radar

The middle pulse repetition frequency（MPRF）and high pulse repetition frequency（HPRF）modes are widely adopted in airborne pulse Doppler（PD）radar systems,which results in the problem that the range measurement of targets is ambiguous.The existing data processing based range ambiguity resolving methods work well on the condition that the signal-to-noise ratio（SNR）is high enough.In this paper,a multiple model particle flter（MMPF）based track-beforedetect（TBD）method is proposed to address the problem of target detection and tracking with range ambiguous radar in low-SNR environment.By introducing a discrete variable that denotes whether a target is present or not and the discrete pulse interval number（PIN）as components of the target state vector,and modeling the incremental variable of the PIN as a three-state Markov chain,the proposed algorithm converts the problem of range ambiguity resolving into a hybrid state fltering problem.At last,the hybrid fltering problem is implemented by a MMPF-based TBD method in the Bayesian framework.Simulation results demonstrate that the proposed Bayesian approach can estimate target state as well as the PIN simultaneously,and succeeds in detecting and tracking weak targets with the range ambiguous radar.Simulation results also show that the performance of the proposed method is superior to that of the multiple hypothesis（MH）method in low-SNR environment.

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter（RSD-ADC） is presented featuring a high signal to noise ratio（SNR）, spurious free dynamic range（SFDR） and signal to noise plus distortion（SNDR） with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC（residue amplification circuit）stages. With the proposed architecture of ADC, SNDR obtained is 85.89 d B, SNR is 85.9 d B and SFDR obtained is 102.8 d B at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.