An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and th...An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging（or discharging） the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.展开更多
基金Project supported by the National Natural Science Foundation of China(Nos.61401137,61404043,61674049)
文摘An ultra-low power output-capacitorless low-dropout（LDO） regulator with a slew-rate-enhanced（SRE）circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging（or discharging） the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 m A and the corresponding variation of output voltage is less than 40 m V. Moreover, the measured line regulation and load regulation are 15.38 m V/V and 0.4 m V/m A respectively.
