The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be...The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.展开更多
A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To ...A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfignration analysis of algorithms, the design of reconfignrable processing units and a new reconfignrable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the opcrating fiequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.展开更多
文摘The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.
文摘A reconfigurable cipher chip for accelerating DES is described, 3DES and AES computations that demand high performance and flexibility to accommodate large numbers of secure connections with heterogeneous clients. To obtain high throughput, we analyze the feasibility of high-speed reconfigurable design and find the key parameters affecting throughput. Then, the corresponding design, which includes the reconfignration analysis of algorithms, the design of reconfignrable processing units and a new reconfignrable architecture based on pipeline and parallel structure, are proposed. The implementation results show that the opcrating fiequency is 110 MHz and the throughput rate is 7 Gbps for DES, 2.3 Gbps for 3 DES and 1.4 Gbps for AES. Compared with the similar existing implementations, our design can achieve a higher performance.
