The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be...The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.展开更多
SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programm...SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.展开更多
文摘The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.
基金supported by the Major Special Projects on National Medium and Long-term Science and Technology Development Planning
文摘SRAM(static random access memory)-based FPGA(field programmable gate array), owing to its large capacity, high performance, and dynamical reconfiguration, has become an attractive platform for So PC(system on programmable chip) development. However, as the configuration memory and logic memory of the SRAM-based FPGA are highly susceptible to SEUs(single-event upsets) in deep space, it is a challenge to design and implement a highly reliable FPGA-based system for spacecraft, and no practical architecture has been proposed. In this paper, a new architecture for a reliable and reconfigurable FPGAbased computer in a highly critical GNC(guidance navigation and control) system is proposed. To mitigate the effect of an SEU on the system, multi-layer reconfiguration and multi-layer TMR(triple module redundancy) techniques are proposed, with a reliable reconfigurable real-time operating system(Space OS) managing the system level fault tolerance of the computer in the architecture. The proposed architecture for the reconfigurable FPGA-based computer has been implemented with COTS(commercial off the shelf) FPGA and has firstly been applied to the GNC system of a circumlunar return and reentry flight vehicle. The in-orbit results show that the proposed architecture is capable of meeting the requirements of high reliability and high availability, and can provide the expressive varying functionality and runtime flexibility for an FPGA-based GNC computer in deep space.
