Parallel Implementation of the CCSDS Turbo Decoder on GPU

This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)standard.However,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism design.To mitigate this issue,we propose a padding method that inserts several bits before the information frame header.To obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are considered.The presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small modifications.The proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.

Iterative Decoding of Parallel Concatenated Block Codes and Coset Based MAP Decoding Algorithm for F24 Code

A multi dimensional concatenation scheme for block codes is introduced, in which information symbols are interleaved and re encoded for more than once. It provides a convenient platform to design high performance codes with flexible interleaver size. Coset based MAP soft in/soft out decoding algorithms are presented for the F24 code. Simulation results show that the proposed coding scheme can achieve high coding gain with flexible interleaver length and very low decoding complexity.

Parallel Processing Design for LTE PUSCH Demodulation and Decoding Based on Multi-Core Processor

The Long Term Evolution (LTE) system imposes high requirements for dispatching delay.Moreover,very large air interface rate of LTE requires good processing capability for the devices processing the baseband signals.Consequently,the single-core processor cannot meet the requirements of LTE system.This paper analyzes how to use multi-core processors to achieve parallel processing of uplink demodulation and decoding in LTE systems and designs an approach to parallel processing.The test results prove that this approach works quite well.

Erasure-Correction-Enhanced Iterative Decoding for LDPC-RS Product Codes

Low-density parity-check(LDPC)codes are widely used due to their significant errorcorrection capability and linear decoding complexity.However,it is not sufficient for LDPC codes to satisfy the ultra low bit error rate(BER)requirement of next-generation ultra-high-speed communications due to the error floor phenomenon.According to the residual error characteristics of LDPC codes,we consider using the high rate Reed-Solomon(RS)codes as the outer codes to construct LDPC-RS product codes to eliminate the error floor and propose the hybrid error-erasure-correction decoding algorithm for the outer code to exploit erasure-correction capability effectively.Furthermore,the overall performance of product codes is improved using iteration between outer and inner codes.Simulation results validate that BER of the product code with the proposed hybrid algorithm is lower than that of the product code with no erasure correction.Compared with other product codes using LDPC codes,the proposed LDPC-RS product code with the same code rate has much better performance and smaller rate loss attributed to the maximum distance separable(MDS)property and significant erasure-correction capability of RS codes.

Turbo Decoding中BCJR算法的应用及改进

并行级连卷积码 (Turbo Codes)是近年来在编码理论上的一个重大突破 ,其性能与信道容量极限的差距可小于 1d B,有着极其广阔的应用前景 ,而其独特的迭代译码方法更成了编码界和通信界讨论的热点。讨论了 Turbo Codes的编译码原理及 BCJR算法 ,比较了 SOVA,M- BCJR及T- BJCR等几种简化译码算法的性能 ,并对后两者的工程应用进行了探讨。

High Speed Versatile Reed-Solomon Decoder for Correcting Errors and Erasures

A new Chien search method for shortened Reed-Solomon （RS） code is proposed, based on this, a versatile RS decoder for correcting both errors and erasures is designed. Compared with the traditional RS decoder, the weighted coefficient of the Chien search method is calculated sequentially through the three pipelined stages of the decoder. And therefore, the computation of the errata locator polynomial and errata evaluator polynomial needs to be modified. The versatile RS decoder with minimum distance 21 has been synthesized in the Xilinx Virtex-Ⅱ series field programmable gate array （FPGA） xe2v1000-5 and is used by coneatenated coding system for satellite communication. Results show that the maximum data processing rate can be up to 1.3 Gbit/s.

A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput （40-100 Mbps）, the hardware cost is still affordable for 3GPP＇s （3rd generation partnership project） interleaver.

Multiple-Symbol Interleaved RS Codes and Two-Pass Decoding Algorithm

For communication systems with heavy burst noise, an optimal Forward Error Correction(FEC) scheme is expected to have a large burst error correction capability while simultaneously owning moderate random error correction capability. This letter presents a new FEC scheme based on multiple-symbol interleaved Reed-Solomon codes and an associated two-pass decoding algorithm. It is shown that the proposed multi-symbol interleaved Reed-Solomon scheme can achieve nearly twice as much as the burst error correction capability of conventional single-symbol interleaved Reed-Solomon codes with the same code length and code rate.

A Highly Compatible Circular-Shifting Network for Partially Parallel QC-LDPC Decoder

The conventional methodology for designing QC-LDPC decoders is applied for fixed configurations used in wireless communication standards, and the supported largest expansion factor Z (the parallelism of the layered decoding) is a fixed number. In this paper, we study the circular-shifting network for decoding LDPC codes with arbitrary Z factor, especially for decoding large Z (Z P) codes, where P is the decoder parallelism. By buffering the P-length slices from the memory, and assembling the shifted slices in a fixed routine, the P-parallelism shift network can process Z-parallelism circular-shifting tasks. The implementation results show that the proposed network for arbitrary sized data shifting consumes only one times of additional resource cost compared to the traditional solution for only maximum P sized data shifting, and achieves significant saving on area and routing complexity.

Modified overlapped partly parallel decode for AR4JA codes in deep space communication

In this paper, according to the AR4JA codes in deep space communication, two kinds of iterative decoding including partly parallel decoding and overlapped partly parallel decoding are analyzed, and the advantages and disadvantages of them are listed. A modified overlapped partly parallel decoding that not only inherits the advantages of the two algorithms, but also overcomes the shortcomings of the two algorithms is proposed. The simulation results show that the three kinds of decoding have the same decoding performance; modified overlapped partly parallel decoding improves the iterative convergence rate and the throughput of system.

A Novel Decoder Based on Parallel Genetic Algorithms for Linear Block Codes

Genetic algorithms offer very good performances for solving large optimization problems, especially in the domain of error-correcting codes. However, they have a major drawback related to the time complexity and memory occupation when running on a uniprocessor computer. This paper proposes a parallel decoder for linear block codes, using parallel genetic algorithms (PGA). The good performance and time complexity are confirmed by theoretical study and by simulations on BCH(63,30,14) codes over both AWGN and flat Rayleigh fading channels. The simulation results show that the coding gain between parallel and single genetic algorithm is about 0.7 dB at BER = 10﹣5 with only 4 processors.

ERASED-CHASE DECODING FOR RS-CODED MPSK SIGNALING OVER A RAYLEIGH FADING CHANNEL

In this paper,a novel dual-metric,the maximum and minimum Squared Euclidean Distance Increment (SEDI) brought by changing the hard decision symbol,is introduced to measure the reli-ability of the received M-ary Phase Shift Keying (MPSK) symbols over a Rayleigh fading channel. Based on the dual-metric,a Chase-type soft decoding algorithm,which is called erased-Chase algorithm,is developed for Reed-Solomon (RS) coded MPSK schemes. The proposed algorithm treats the unre-liable symbols with small maximum SEDI as erasures,and tests the non-erased unreliable symbols with small minimum SEDI as the Chase-2 algorithm does. By introducing optimality test into the decoding procedure,much more reduction in the decoding complexity can be achieved. Simulation results of the RS(63,42,22)-coded 8-PSK scheme over a Rayleigh fading channel show that the proposed algorithm provides a very efficient tradeoff between the decoding complexity and the error performance. Finally,an adaptive scheme for the number of erasures is introduced into the decoding algorithm.

基于情感语义增强编解码的神经机器翻译方法

针对目前神经机器翻译模型仅依赖平行语料训练而无法充分挖掘深层语言知识的问题,提出一种基于情感语义增强编解码的神经机器翻译方法,旨在通过引入额外的情感语义,提高模型对语言深层次信息的理解能力。首先,利用word2vec技术获取语料中所有单词的词嵌入,将其输入到一个融合模型中进行训练。该融合模型结合了基于GRU和文档嵌入的机制,以获取单词级别和文档级别的情感语义表征;其次,在情感融合阶段,采用加权公式将单词级别和文档级别的情感语义有机地融合,形成更为综合的情感语义表征;最后,将此表征与上下文语义表征按位相加,以全面引入情感信息,并将其作为输入传递到机器翻译模型的编码器和解码器中。在多个基准数据集上的实验显示,相较于传统的Transformer模型,该方法在IWSLT数据集上性能显著提升,BLEU值增加1.3至1.62。在WMT数据集上也取得良好性能,证实了融合情感语义在机器翻译中的有效性。

截短Reed-Solomon码译码器的FPGA实现

提出了一种改进的BM算法,并在此基础上提出了一种大量采用并行结构的截短RS码译码器的实现方式。验证表明,该算法能显著提高基于FPGA的RS译码器的速度并简化其电路结构。

面向软件无线电的物理下行共享信道优化与实现

针对软件无线电平台Open Air Interface(OAI)终端侧物理下行共享信道(Physical Downlink Shared Channel,PDSCH)中解扰模块和信道译码模块数据延时大的问题,提出了基于图形处理单元(Graphic Processing Unit,GPU)中统一计算设备架构的PDSCH优化方案,对传输块进行比特级和码块级数据划分,设计了多GPU下的并行解扰和并行信道译码,降低了数据延时,提高了下行峰值速率。实验结果表明,该优化方案基本维持了原有循环冗余校验码错误率,且在不同传输块大小下,解扰模块耗时最大降低92.1%,信道译码模块耗时最大降低83.7%,终端PDSCH耗时最大降低77.8%,下行峰值速率最大提高138.3%,有效提升了OAI平台性能。

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

基于双集合预测网络的实体关系联合抽取模型

实体关系抽取任务旨在从非结构化文本中识别出实体和实体间的关系,是目前大规模知识图谱构建和更新的技术来源。在现有的实体关系联合抽取方法中,并行解码三元组的方法通过集合预测的方式高效生成三元组,然而这种方法忽略了实体与关系间、实体主客体间的交互,导致生成无效三元组。针对此问题,提出基于双集合预测网络的实体关系联合抽取模型。为了增强关系和实体之间的交互,采用双集合预测网络并行解码三元组,顺序生成三元组中实体信息和关系类型:第一个集合预测网络对三元组集合建模并解码出三元组内的主客体信息,第二个集合预测网络对融合了主客体信息的三元组嵌入集合建模并解码出主客体间的关系类型;针对实体主客体设计了一个实体过滤器,预测句子中实体间的主客体相关性并依照该结果过滤掉主客体相关性较低的三元组。在公开数据集纽约时报(NYT)和WebNLG上的实验结果表明,在编码器为BERT的情况下所提模型相较基线模型在准确率和F1指标上的效果更好,验证了该模型的有效性。

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.

Design and Implementation of Single Chip WCDMA High Speed Channel Decoder

A memory and driving clock efficient design scheme to achieve WCDMA high-speed channel decoder on a single XILINX’ XVC1000E FPGA chip is presented. Using a modified MAP algorithm, say parallel Sliding Window logarithmic Maximum A Posterior (PSW-log-MAP), the on-chip turbo decoder can decode an information bit by only an average of two clocks per iteration. On the other hand, a high-parallel pipeline Viterbi algorithm is adopted to realize the 256-state convolutional code decoding. The final decoder with an 8×chip-clock (30 72MHz) driving can concurrently process a data rate up to 2 5Mbps of turbo coded sequences and a data rate over 400kbps of convolutional codes. There is no extern memory needed. Test results show that the decoding performance is only 0 2～0 3dB or less lost comparing to float simulation.