Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed an...Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.展开更多
Circuit Emulation Service(CES)aims to enable packet switched networks to provide guaranteed services with comparable qualities of circuit switched networks.Our paper addresses the key issue of QoS of CES flows over In...Circuit Emulation Service(CES)aims to enable packet switched networks to provide guaranteed services with comparable qualities of circuit switched networks.Our paper addresses the key issue of QoS of CES flows over Internet.Enlightened by the time division idea popularly used in circuit switched networks,we propose a time division based control mechanism to provide guaranteed QoS for the constant-rate CES flows.The control mechanism is able to estimate the arrival times of the coming packets in CES flows,and reserve the time slots for them.Accordingly,it enables the packets to consume the reserved time slots of their own,so the CES flows are guaranteed to be processed.Refreshing Bloom Filter(RBF),an efficient data representation structure,is proposed to support the time division control mechanism.It consists of multiple bloom filters,and can efficiently record the arrival time slots of millions of packets.The proposed control system model could be a practical tool to support Circuit Emulation Services over Internet.展开更多
文摘Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.
文摘Circuit Emulation Service(CES)aims to enable packet switched networks to provide guaranteed services with comparable qualities of circuit switched networks.Our paper addresses the key issue of QoS of CES flows over Internet.Enlightened by the time division idea popularly used in circuit switched networks,we propose a time division based control mechanism to provide guaranteed QoS for the constant-rate CES flows.The control mechanism is able to estimate the arrival times of the coming packets in CES flows,and reserve the time slots for them.Accordingly,it enables the packets to consume the reserved time slots of their own,so the CES flows are guaranteed to be processed.Refreshing Bloom Filter(RBF),an efficient data representation structure,is proposed to support the time division control mechanism.It consists of multiple bloom filters,and can efficiently record the arrival time slots of millions of packets.The proposed control system model could be a practical tool to support Circuit Emulation Services over Internet.
