Modeling of photolithography process in semiconductor wafer fabrication systems using extended hybrid Petri nets

To describe a semiconductor wafer fabrication flow availably, a new modeling method of extended hybrid Petri nets （EHPNs） was proposed. To model the discrete part and continuous part of a complex photolithography process, hybrid Petri nets （HPNs） were introduced. To cope with the complexity of a photolithography process, object-oriented methods such as encapsulation and classifications were integrated with HPN models. EHPN definitions were presented on the basis of HPN models and object-oriented methods. Object-oriented hybrid Petri subnet models were developed for each typical physical object and an EHPN modeling procedure steps were structured. To demonstrate the feasibility and validity of the proposed modeling method, a real wafer photolithography case was used to illustrate the modeling procedure. dynamic modeling of a complex photolithography process effectively The modeling results indicate that the EHPNs can deal with the dynamic modeling of a complex photolithography process effectively.

用5微米工艺设备加工1～2微米窄条的光刻技术

本文介绍了利用现有5μm工艺设备进行1～2μm窄条的光刻技术,着重对光刻SiO_2窄条和金属连线方面作了具体的介绍。对优化的“发射区两次错位光刻”和“多晶发射极自对准”工艺技术作了较详细的叙述。

表面等离子体无掩膜干涉光刻系统的数值分析(英文)

表面等离子体激元具有近场增强效应,可以代替光子作为曝光源形成纳米级特征尺寸的图像.本文数值分析了棱镜辅助表面等离子体干涉系统的参量空间,并给出了计算原理和方法.结果表明,适当地选择高折射率棱镜、低银层厚度、入射波长和光刻胶折射率,可以获得高曝光度、高对比度的干涉图像.入射波长为431nm时,选择40nm厚的银层,曝光深度可达200nm,条纹周期为110nm.数值分析结果为实验的安排提供了理论支持.

计算光刻研究及进展

光刻是将集成电路器件的结构图形从掩模转移到硅片或其他半导体基片表面上的工艺过程,是实现高端芯片量产的关键技术。在摩尔定律的推动下,光刻技术跨越了90~7 nm及以下的多个工艺节点,逐步逼近其分辨率的物理极限。同时,光刻系统的衍射受限特性,以及各类系统像差、误差和工艺偏差,都会严重影响光刻成像精度。此时,必须采用计算光刻技术来提高光刻成像分辨率和图形保真度。计算光刻是涉及光学、半导体技术、计算科学、图像与信号处理、材料科学、信息学等多个专业的交叉研究领域。它以光学成像和工艺建模为基础,采用数学方法对光刻成像过程进行全链路的仿真与优化,实现成像误差的高精度补偿,能够有效提升工艺窗口和芯片制造良率,降低光刻工艺的研发周期与成本,目前已成为高端芯片制程的核心环节之一。本文首先简单介绍了计算光刻的前身,即传统的分辨率增强技术,在此基础上介绍了计算光刻的基本原理、模型和算法。之后对光学邻近效应校正、光源优化和光源掩模联合优化三种常用的计算光刻技术进行了综述,总结了相关的研究进展、成果和应用。最后,阐述了计算光刻当前所面临的需求与挑战,并讨论了最新技术进展和未来发展方向。