Design of a 14-Bit 1 MS/s Successive Approximation Analog-to-Digital Converter

A 14-bit successive approximation analog-to-digital converter (SAR ADC) with capacitive calibration has been designed based on the SMIC. 18 μm CMOS process. The overall architecture is in fully differential form to eliminate the effect caused by common mode noise. Meanwhile, the digital-to-analog converter (DAC) is a two-stage structure, which can greatly reduce the area of the capacitor array compared with the traditional DAC structure. The capacitance calibration module is mainly divided into the mismatch voltage acquisition phase and the calibration code backfill phase, which effectively reduces the impact of the DAC mismatch on the accuracy of the SAR ADC. The design of this paper is based on cadence platform simulation verification, simulation results show that when the sampling rate is 1 MS/s, the power supply voltage is 5 V and the reference voltage is 4.096 V, the effective number of bits (ENOB) of the ADC is 13.49 bit, and the signal-to-noise ratio (SNR) is 83.3 dB.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

A 71mW 8b 125MSample/s A/D Converter

A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.

A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter

A novel low-voltage,low constant-impedance switch is proposed, which not only eliminates the parasitic capacitor but also reduces the variation of switch ＂on＂ resistance. With the gain-boost technology,the operational transconductance amplifier used in this analog-to-digital converter （ADC） achieves enough DC gain and unity-gain frequency under the low voltage supply and to guarantee the performance of the sample and hold circuit （S/H） and the sub-stages. Based on these methods,a 10bit 100Msps pipelined ADC is fabricated in a 0. 18μm CMOS process and operates under a 1.8V voltage supply. The ADC achieves an SNR of 54. 2dB （input frequency of 6.26MHz） and an SNR of 49. 8dB （input frequency of 48. 96MHz） when the sampling frequency is 100MHz.

200Ms/s 177mW 8bit Folding and Interpolating CMOS A/D Converter

A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.

一种16位110 dB无杂散动态范围的低功耗SAR ADC

该文设计了一款16位、转换速率为625 kS/s的逐次逼近寄存器型模数转换器(SAR ADC)。改进的采样保持电路结构,优化了采样线性度和噪声性能。采用分段结构设计电容型数模转换器并使用混合方式的电容切换方案,减小面积和能耗。利用扰动注入技术提升ADC的线性度。比较器采用两级积分型预放大器减小噪声,利用输出失调存储技术及优化的电路设计减小了比较器失调电压和失调校准引入的噪声,优化并提升了比较器速度。芯片采用CMOS 0.18μm工艺设计和流片,ADC核心面积为1.15 mm^(2)。测试结果表明,在1 kHz正弦信号输入下,ADC差分输入峰峰值幅度达8.8 V,信纳比为85.9 dB,无杂散动态范围为110 dB,微分非线性为-0.27/+0.32 LSB,积分非线性为-0.58/+0.53 LSB,功耗为4.31 mW。

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

高精度低功耗噪声整形SAR ADC设计

针对传统无源有损积分环路滤波器相较于有源无损积分环路滤波器,具有功耗低、电路设计简单等特点,但其噪声传输函数(NTF:Noise Transfer Function)平滑,噪声整形效果较弱的问题,提出了一种无源无损的二阶积分环路滤波器,保留了无源有损积分优点的同时具有良好噪声整形效果。设计了一款分辨率为16 bit、采样率为2 Ms/s的混合架构噪声整形SAR ADC。仿真结果表明,在125 kHz带宽、过采样比为8时,实现了高信号与噪声失真比(SNDR(Signal to Noise and Distortion Ratio)为91.1 dB)、高精度(14.84 bit)和低功耗(285μW)的性能。

可重配置无源噪声整形SAR模数转换器设计

随着工业技术的提升,对模数转换器在精度与功耗上的要求日益增高。凭借噪声整形模数转换器的卓越性能,设计了一种可重配置的18位噪声整形的逐次逼近寄存器型模数转换器(SAR ADC)电路,利用SMIC 40 nm工艺实现,并通过仿真验证其理想模型,旨在探索其在物联网等领域的应用潜力。实验结果显示,该模数转换器在标准配置下以1 MS/s吞吐率实现了17.4位的有效位数,展现了高精度特性;通过重配置,其可切换至低功耗高速模式,吞吐率提升至5 MS/s,同时保持11.99位的有效精度,平衡了性能与功耗。这一可重配置设计不仅满足了高精度低功耗的需求,还因其灵活性而能广泛适用于多种数据采样场景,为物联网等领域的高性能模数转换器设计提供了创新方案。

SARS-CoVS蛋白功能性受体ACE2在人角膜、结膜中的表达

目的检测人角膜、结膜中血管紧张素转化酶2(ACE 2)的表达,由此来初步推断重症急性呼吸综合征(SARS)冠状病毒由眼部入侵的可能.方法取成人眼球破裂伤摘除的眼角膜和结膜组织及4～6个月中期引产胎儿的眼角膜、结膜、心、肺组织,分别采用RT-PCR和免疫组化方法检测组织中ACE 2的表达.取成人尸体解剖的心、肺组织作为对照.结果在上述各种组织中均检测到了ACE.2的表达.结论眼角膜、结膜是人体暴露于SARS冠状病毒的一个重要部位,研究结果从mRNA和蛋白质水平证实了眼部组织存在SARS冠状病毒S蛋白的功能性受体ACE 2,由此初步推断SARS-CoV存在由眼部入侵的可能,为临床进一步研究SARS的防护和致病机制提供了线索.

SARS-CoVS蛋白功能性受体ACE2在人、兔角膜、结膜中的表达

目的 SARS冠状病毒 (SARS CoV)的S蛋白介导了病毒与宿主细胞的结合 ,最近已鉴定出SARS CoVS蛋白的功能性受体是血管紧张素转化酶 2 (angiotensin convertingenzyme 2 ,ACE2 )。本研究检测了ACE2在人、兔眼结膜、角膜中的表达 ,由此来初步推断SARS CoV由眼部入侵的可能。方法 分别采取 :(1)成人眼球破裂伤摘除的眼角膜和结膜组织 ;(2 ) 4～ 6月中期引产胎儿的眼角膜、结膜、心、肺组织 ;(3)兔眼角膜、结膜、心、肺组织 ;(4 )培养的人结膜成纤维细胞和兔角膜上皮细胞。分别采用RT PCR和免疫组化方法检测各组织、细胞中ACE2的表达。取尸体解剖的成人心、肺组织作为对照。结果 RT PCR法在上述各种组织和细胞中均检测到ACE2的扩增条带 ,其中胎儿、成人和兔的角膜、结膜扩增条带较心、肺稍弱 ,兔各组织的扩增条带亮度与对应的人体组织的扩增条带亮度相近。ACE2免疫组化反应产物主要位于胞浆和胞膜 ,呈棕黄色或棕褐色。角膜和结膜的上皮细胞及角膜内皮细胞呈明显的阳性表达 ,角膜和结膜的成纤维细胞呈弱阳性表达 ,培养的人结膜成纤维细胞和兔角膜上皮细胞亦可见阳性表达。兔组织中的ACE2表达强度及组织定位与人相近。结论 本研究从mRNA和蛋白质水平证实了眼组织存在SARS冠状病毒S蛋白的功能性受体ACE2 ,由?

微型SAR的数字下变频设计

在微型SAR实时成像样机的设计中,对雷达回波在中频进行采样,然后采用数字下变频技术实现正交解调,可以减少系统的复杂性,提高雷达的数字化程度和性能。该文针对微型SAR方案中数字下变频设计中的难点,即采样频率高达2Gsps,带宽900MHz,实时处理的难度很大,根据具体设计参数优化了数字下变频的实现结构,重点比较了并行FIR滤波器和快行FIR滤波器的差别,然后在FPGA中编程实现了数字下变频模块,给出资源占用情况、运行速度和量化噪声影响,最后给出在微型SAR技术项目中的实际应用结果,理想的成像结果表明了该设计的正确性。

一种10位200kS/s 65nm CMOS SAR ADC IP核

该文基于65nm CMOS低漏电工艺,设计了一种用于触摸屏SoC的8通道10位200kS/s逐次逼近寄存器型(Successive Approximation Register,SAR)A/D转换器(Analog-to-Digital Converter,ADC)IP核。在D/A转换电路的设计上,采用"7MSB(Most-Significant-Bit)+3LSB(Least-Significant-Bit)"R-C混合D/A转换方式,有效减小了IP核的面积,并通过采用高位电阻梯复用技术有效减小了系统对电容的匹配性要求。在比较器的设计上,通过采用一种低失调伪差分比较技术,有效降低了输入失调电压。在版图设计上,结合电容阵列对称布局以及电阻梯伪电阻包围的版图设计方法进行设计以提高匹配性能。整个IP核的面积为322μm×267μm。在2.5V模拟电压以及1.2V数字电压下,当采样频率为200kS/s,输入频率为1.03kHz时,测得的无杂散动态范围(Spurious-Free Dynamic Range,SFDR)和有效位数(Effective Number Of Bits,ENOB)分别为68.2dB和9.27,功耗仅为440μW,测试结果表明本文ADC IP核非常适合嵌入式系统的应用。

SARS冠状病毒S蛋白的功能性受体-ACE2

SARS冠状病毒的棘突S蛋白 ,与细胞受体介导的感染有关。血管紧张素转化酶 2 (ACE2 )是SARS CoVS蛋白的功能性受体 ,人类ACE2酶的细胞外区域由 2个亚基组成 ,其中锌金属肽酶区域可以进一步分成 2个亚域 (I和II) ,形成一个长而深的裂缝 ,环绕裂缝顶端的隆起线可能作为与S 糖蛋白结合的区域。ACE2可以与SARS CoVS蛋白的S3 1 8 5 1 0结合。这将为发展新型SARS疫苗和SARS的预防和治疗提供新的研究方向。