随着二维码技术广泛应用于电子票务、银行支票、电子保单等多个领域,二维码的信息泄露和信息篡改等安全问题日益突出.为提高二维码内部信息的安全性能,从对二维码内部信息加密和二维码信息防篡改俩个角度来提高.基于Visual Studio 2008...随着二维码技术广泛应用于电子票务、银行支票、电子保单等多个领域,二维码的信息泄露和信息篡改等安全问题日益突出.为提高二维码内部信息的安全性能,从对二维码内部信息加密和二维码信息防篡改俩个角度来提高.基于Visual Studio 2008 C#平台,设计了一种采用SHA512哈希函数和Rijndael加密算法混合加密的方法,该方法利用Rijndael加密和SHA512数字签名等技术,对Rijndael第一次加密密钥系统随机分配,并对系统随机分配密钥采用二次Rijndael加密防护方法,并通过SHA512对二维码内部信息防篡改校验,达到对二维码信息及其加密密钥的安全保护.在生成QR二维码之前实现了信息加密,并从系统构架、算法原理和实现及安全性能等多个方面进行了测试和分析.分析表明此方法提高了二维码信息的安全性能,达到对密钥高效管理和对信息的多重保护,而在加密后密文信息容量较明文信息有所增加.展开更多
In order to meet the needs of higher operation speed and lower energy consumption an optimized SHA-1 algorithm is proposed.It combines two methods loop-unfolding and pre-processing.In the process intermediate variable...In order to meet the needs of higher operation speed and lower energy consumption an optimized SHA-1 algorithm is proposed.It combines two methods loop-unfolding and pre-processing.In the process intermediate variables are introduced in the iterations and pre-calculated so that the original single-threading operation can perform in a multi-threading way.This optimized algorithm exploits parallelism to shorten the critical path for hash operations.And the cycles of the original algorithm are reduced from 80 to 41 which greatly improves the operation speed.Therefore the shortened iterations of the optimized design require a smaller amount of hardware resource thus achieving a lower energy consumption. The optimized algorithm is implemented on FPGA field programmable gate array .It can achieve a throughput rate of 1.2 Gbit /s with the maximum clock frequency of 91 MHz reaching a fair balance between operation speed and throughput rate.The simulation results show that compared with other optimized SHA-1 algorithms this algorithm obtains higher operation speed and throughput rate without compromising the security of the original SHA-1 algorithm.展开更多
An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the...An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.展开更多
文摘随着二维码技术广泛应用于电子票务、银行支票、电子保单等多个领域,二维码的信息泄露和信息篡改等安全问题日益突出.为提高二维码内部信息的安全性能,从对二维码内部信息加密和二维码信息防篡改俩个角度来提高.基于Visual Studio 2008 C#平台,设计了一种采用SHA512哈希函数和Rijndael加密算法混合加密的方法,该方法利用Rijndael加密和SHA512数字签名等技术,对Rijndael第一次加密密钥系统随机分配,并对系统随机分配密钥采用二次Rijndael加密防护方法,并通过SHA512对二维码内部信息防篡改校验,达到对二维码信息及其加密密钥的安全保护.在生成QR二维码之前实现了信息加密,并从系统构架、算法原理和实现及安全性能等多个方面进行了测试和分析.分析表明此方法提高了二维码信息的安全性能,达到对密钥高效管理和对信息的多重保护,而在加密后密文信息容量较明文信息有所增加.
基金The Project of Wireless Intelligence Terminal Inspection Services(No.6704000084)the Special Program of the NationalDevelopment and Reform Committee
文摘In order to meet the needs of higher operation speed and lower energy consumption an optimized SHA-1 algorithm is proposed.It combines two methods loop-unfolding and pre-processing.In the process intermediate variables are introduced in the iterations and pre-calculated so that the original single-threading operation can perform in a multi-threading way.This optimized algorithm exploits parallelism to shorten the critical path for hash operations.And the cycles of the original algorithm are reduced from 80 to 41 which greatly improves the operation speed.Therefore the shortened iterations of the optimized design require a smaller amount of hardware resource thus achieving a lower energy consumption. The optimized algorithm is implemented on FPGA field programmable gate array .It can achieve a throughput rate of 1.2 Gbit /s with the maximum clock frequency of 91 MHz reaching a fair balance between operation speed and throughput rate.The simulation results show that compared with other optimized SHA-1 algorithms this algorithm obtains higher operation speed and throughput rate without compromising the security of the original SHA-1 algorithm.
基金supported by National Natural Science Foundation of China with granted No.61404175
文摘An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs.
