2014年3月，早春的上海，突然造访的Synopsys公司董事长兼全球联合首席执行官Aart de Geus博士在这里面向中国大陆的专业媒体，率先做了一系列针对IC设计、验证和仿真的重要产品发布，为面对复杂SoC芯片设计的工程师解决挑战提供了全新...2014年3月，早春的上海，突然造访的Synopsys公司董事长兼全球联合首席执行官Aart de Geus博士在这里面向中国大陆的专业媒体，率先做了一系列针对IC设计、验证和仿真的重要产品发布，为面对复杂SoC芯片设计的工程师解决挑战提供了全新的解决方案。展开更多
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog...This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.展开更多
文摘This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
