随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了...随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。展开更多
Dynamic self-heating effect(SHE)of silicon-on-insulator(SOI)MOSFET is comprehensively evaluated by ultrafast pulsed I-V measurement in this work.It is found for the first time that the SHE complete heating response an...Dynamic self-heating effect(SHE)of silicon-on-insulator(SOI)MOSFET is comprehensively evaluated by ultrafast pulsed I-V measurement in this work.It is found for the first time that the SHE complete heating response and cooling response of SOI MOSFETs are conjugated,with two-stage curves shown.We establish the effective thermal transient response model with stage superposition corresponding to the heating process.The systematic study of SHE dependence on workload shows that frequency and duty cycle have more significant effect on SHE in first-stage heating process than in the second stage.In the first-stage heating process,the peak lattice temperature and current oscillation amplitude decrease by more than 25 K and 4%with frequency increasing to 10 MHz,and when duty cycle is reduced to 25%,the peak lattice temperature drops to 306 K and current oscillation amplitude decreases to 0.77%.Finally,the investigation of two-stage(heating and cooling)process provides a guideline for the unified optimization of dynamic SHE in terms of workload.As the operating frequency is raised to GHz,the peak temperature depends on duty cycle,and self-heating oscillation is completely suppressed.展开更多
Distortion analysis of SOI MOS transistor is presented.By the power series method,the distortion behaviors of FD (fully depleted) and RC (recessed channel) SOI MOS transistor configurations are investigated.It is show...Distortion analysis of SOI MOS transistor is presented.By the power series method,the distortion behaviors of FD (fully depleted) and RC (recessed channel) SOI MOS transistor configurations are investigated.It is shown that the distortion figures deteriorate with the scaling down of channel length,and the RC SOI device shows better distortion performance than the FD SOI device.At the same time,the experimental data show that the ineffective body contact can lead to an increase of the harmonic amplitude due to the bulk resistance.The presented results give an intuitive knowledge for the design of low distortion mixed signal integrated system.展开更多
A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving...A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving the 2D Poisson＇s equation. The minimum of the potential at the oxide-Si layer interface is used to monitor the threshold voltage of the SOI MOSFETs. This model is verified by its excellent agreement with MEDICI simulation using SOI MOSFETs with different gate lengths,gate oxide thicknesses,silicon film thicknesses,and channel doping concentrations.展开更多
Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristic...Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristics and the breakdown voltage are studied in detail. Through simulations,it is found that the AC PD SOI device can suppress the floating effects and improve the breakdown characteristics over conventional partially depleted silicon-on-insulator devices. Also compared to the reported AC FD SOI device,the performance variation with device parameters is more predictable and operable in industrial applications. The AC FD SO1 device has thinner silicon film, which causes parasitical effects such as coupling effects between the front gate and the back gate and hot electron degradation effects.展开更多
A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with ...A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.展开更多
文摘随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。
文摘Dynamic self-heating effect(SHE)of silicon-on-insulator(SOI)MOSFET is comprehensively evaluated by ultrafast pulsed I-V measurement in this work.It is found for the first time that the SHE complete heating response and cooling response of SOI MOSFETs are conjugated,with two-stage curves shown.We establish the effective thermal transient response model with stage superposition corresponding to the heating process.The systematic study of SHE dependence on workload shows that frequency and duty cycle have more significant effect on SHE in first-stage heating process than in the second stage.In the first-stage heating process,the peak lattice temperature and current oscillation amplitude decrease by more than 25 K and 4%with frequency increasing to 10 MHz,and when duty cycle is reduced to 25%,the peak lattice temperature drops to 306 K and current oscillation amplitude decreases to 0.77%.Finally,the investigation of two-stage(heating and cooling)process provides a guideline for the unified optimization of dynamic SHE in terms of workload.As the operating frequency is raised to GHz,the peak temperature depends on duty cycle,and self-heating oscillation is completely suppressed.
文摘Distortion analysis of SOI MOS transistor is presented.By the power series method,the distortion behaviors of FD (fully depleted) and RC (recessed channel) SOI MOS transistor configurations are investigated.It is shown that the distortion figures deteriorate with the scaling down of channel length,and the RC SOI device shows better distortion performance than the FD SOI device.At the same time,the experimental data show that the ineffective body contact can lead to an increase of the harmonic amplitude due to the bulk resistance.The presented results give an intuitive knowledge for the design of low distortion mixed signal integrated system.
文摘A new two-dimensional （2D） analytical model for the threshold-voltage of fully depleted SOI MOSFETs is derived. The 2D potential distribution functions in the active layer of the devices are obtained through solving the 2D Poisson＇s equation. The minimum of the potential at the oxide-Si layer interface is used to monitor the threshold voltage of the SOI MOSFETs. This model is verified by its excellent agreement with MEDICI simulation using SOI MOSFETs with different gate lengths,gate oxide thicknesses,silicon film thicknesses,and channel doping concentrations.
文摘Asymmetric doping channel （AC） partially depleted （PD） silicon-on-insulator （SOI） devices are simulated using two-dimensional simulation software. The electrical characteristics such as the output characteristics and the breakdown voltage are studied in detail. Through simulations,it is found that the AC PD SOI device can suppress the floating effects and improve the breakdown characteristics over conventional partially depleted silicon-on-insulator devices. Also compared to the reported AC FD SOI device,the performance variation with device parameters is more predictable and operable in industrial applications. The AC FD SO1 device has thinner silicon film, which causes parasitical effects such as coupling effects between the front gate and the back gate and hot electron degradation effects.
基金Project 60472003 supported by National Natural Science Foundation of China and 2005CB321701 by the State Key Development Program for BasicResearch of China
文摘A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.
