UTBB SOI MOSFETs短沟道效应抑制技术

随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。

Analytical workload dependence of self-heating effect for SOI MOSFETs considering two-stage heating process

Dynamic self-heating effect(SHE)of silicon-on-insulator(SOI)MOSFET is comprehensively evaluated by ultrafast pulsed I-V measurement in this work.It is found for the first time that the SHE complete heating response and cooling response of SOI MOSFETs are conjugated,with two-stage curves shown.We establish the effective thermal transient response model with stage superposition corresponding to the heating process.The systematic study of SHE dependence on workload shows that frequency and duty cycle have more significant effect on SHE in first-stage heating process than in the second stage.In the first-stage heating process,the peak lattice temperature and current oscillation amplitude decrease by more than 25 K and 4%with frequency increasing to 10 MHz,and when duty cycle is reduced to 25%,the peak lattice temperature drops to 306 K and current oscillation amplitude decreases to 0.77%.Finally,the investigation of two-stage(heating and cooling)process provides a guideline for the unified optimization of dynamic SHE in terms of workload.As the operating frequency is raised to GHz,the peak temperature depends on duty cycle,and self-heating oscillation is completely suppressed.

Investigation of temperature-dependent small-signal performances of TB SOI MOSFETs

This paper investigated the temperature dependence of the cryogenic small-signal ac performances of multi-finger partially depleted（PD） silicon-on-insulator（SOI） metal oxide semiconductor field effect transistors（MOSFETs）,with T-gate body contact（TB） structure.The measurement results show that the cut-off frequency increases from 78 GHz at 300 K to 120 GHz at 77 K and the maximum oscillation frequency increases from 54 GHz at 300 K to 80 GHz at 77 K,and these are mainly due to the effect of negative temperature dependence of threshold voltage and transconductance.By using a simple equivalent circuit model,the temperature-dependent small-signal parameters are discussed in detail.The understanding of cryogenic small-signal performance is beneficial to develop the PD SOI MOSFETs integrated circuits for ultra-low temperature applications.

热载流子诱生MOSFET/SOI界面陷阱的正向栅控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究 .正向栅控二极管技术简单、准确 ,可以直接测得热载流子诱生的平均界面陷阱密度 ,从而表征器件的抗热载流子特性 .实验结果表明 :通过体接触方式测得的MOSFET/SOI栅控二极管R G电流峰可以直接给出诱生的界面陷阱密度 .抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系 ,指数因子约为 0

深亚微米薄层SOI/MOSFET’s热载流子效应分析

本文从二维模拟热载流子注入电流入手，讨论了不同硅层厚度、栅氧厚度和掺杂浓度对薄层深亚微米ＳＯＩ／ＭＯＳＦＥＴ’ｓ热载流子效应的影响．模拟结果表明，对于不同的硅层厚度，沟道前表面漏结处的载流子浓度对热载流子效应起着不同的作用，有时甚至是决定性的作用．沟道前表面漏结处的载流子浓度和沟道最大电场一样，是影响薄层ＳＯＩ／ＭＯＳＦＥＴ’ｓ热载流子效应的重要因素，这也就解释了以往文献中，随着硅层减薄，沟道电场增大，热载流子效应反而减小的矛盾．模拟也显示了在一定的硅层厚度变化范围内（６０～１００ｎｍ），器件热载流子效应达到最小值，而且在这一硅层范围内，热载流子效应对硅层厚度、栅氧厚度以及掺杂浓度的变化不敏感，这对高性能深亚微米薄层ＳＯＩ／ＭＯＳＦＥＴ’ｓ设计具有重要的指导意义．

正向栅控二极管监测F- N电应力诱生的SOI- MOSFET界面陷阱(英文)

报道了正向栅控二极管 R- G电流法表征 F- N电应力诱生的 SOI- MOSFET界面陷阱的实验及其结果 .通过体接触的方式实现了实验要求的 SOI- MOSFET栅控二极管结构 .对于逐渐上升的累积应力时间 ,测量的栅控二极管电流显示出明显增加的 R- G电流峰值 .根据 SRH理论的相关公式 ,抽取出来的诱生界面陷阱密度是随累积应力时间的上升而呈幂指数的方式增加 ,指数为 0 .4.

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

纳米MOSFET/SOI器件新结构

重点介绍器件进入纳米尺度后出现的MOSFET/SOI器件的新结构,如超薄SOI器件、双栅MOSFET、FinFET和应变沟道等SOI器件,并对它们的性能进行了分析。

Two-dimensional threshold voltage analytical model of DMG strained-silicon-on-insulator MOSFETs

For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator（DMG SSOI） MOSFETs is developed.We investigate the improved short channel effect（SCE）,hot carrier effect（HCE）,drain-induced barrier-lowering（DIBL） and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a＂rollup＂in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.