A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assu...A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.展开更多
A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on t...A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.展开更多
A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has t...A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.展开更多
A novel triple RESURF(T-resurf) SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and lead...A novel triple RESURF(T-resurf) SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_(sp) is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF(D-resurf) SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_(on).It reduces R_(sp) by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.展开更多
A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Po...A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (VB,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.展开更多
A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of t...A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n+-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n+-regions on the interface by the force with ionized donors in the undepleted n+-regions, and therefore effectively enhance the electric field of the dielectric buried layer (Ei) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.展开更多
A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown character...A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (Er) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.展开更多
An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenc...An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches (DTMOS), an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide (BOX). The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide (eox) than that of Si (esi). Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF (reduced surface field) effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit (HVIC), effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.展开更多
A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of nu...A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.展开更多
基金supported by the National Natural Science Foundation of China(Grant No.61076073)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant No.20133223110003)
文摘A novel one-dimensional(1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field(RESURF) lateral power device fabricated on silicon on an insulator(SOI) substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 60976060)the National Key Laboratory of Analogue Integrated Circuit, China (Grant No. 9140C090304110C0905)
文摘A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator (SOI) trench lateral double-diffused metal-oxide-semiconductor (LDMOS) is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060)the National Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905)
文摘A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.
基金Project supported by the National Natural Science Foundation of China(Nos.60806025,60976060)
文摘A novel triple RESURF(T-resurf) SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_(sp) is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF(D-resurf) SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_(on).It reduces R_(sp) by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.
基金Project supported by the National Natural Science Foundation of China (Grant No 60436030)National Laboratory of Analogue Integrated Circuits,China (Grant No 9140C090305060C09)
文摘A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (VB,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60436030 and 60806025)
文摘A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n+-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n+-regions on the interface by the force with ionized donors in the undepleted n+-regions, and therefore effectively enhance the electric field of the dielectric buried layer (Ei) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.
基金supported by the National Natural Science Foundation of China (Grant Nos. 60806025 and 60976060)the Funds of the National Laboratory of Analog Integrated Circuit (Grant No. 9140C0903070904)the Youth Teacher Foundation of the University of Electronic Science and Technology of China (Grant No. jx0721)
文摘A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (Er) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.
基金Projects supported by the National Natural Science Foundation of China(No.61176069)the Special Financial Gnants from the China Postdoctoral Science Foundation and Chongqing(Nos.2012T50771,XM2012004)
文摘An improved breakdown voltage (BV) SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches (DTMOS), an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide (BOX). The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide (eox) than that of Si (esi). Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF (reduced surface field) effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit (HVIC), effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.
文摘A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF (reduced surface field) structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration (per unit area) of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.