One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

A novel one-dimensional（1D） analytical model is proposed for quantifying the breakdown voltage of a reduced surface field（RESURF） lateral power device fabricated on silicon on an insulator（SOI） substrate.We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions.Based on the assumption,the lateral PN junction behaves as a linearly graded junction,thus resulting in a reduced surface electric field and high breakdown voltage.Using the proposed model,the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools.The analytical results are shown to be in fair agreement with the numerical results.Finally,a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters.This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device.

A new analytical model for the surface electric field distribution and breakdown voltage of the SOI trench LDMOS

A new analytical model for the surface electric field distribution and breakdown voltage of the silicon oil insulator （SOI） trench lateral double-diffused metal-oxide-semiconductor （LDMOS） is presented. Based on the two-dimensional Laplace solution and Poisson solution, the model considers the influence of structure parameters such as the doping concentration of the drift region, and the depth and width of the trench on the surface electric field. Further, a simple analytical expression of the breakdown voltage is obtained, which offers an effective way to gain an optimal high voltage. All the analytical results are in good agreement with the simulation results.

薄膜SOI RESURF结构击穿电压分析

提出了基于二维Ｐｏｉｓｓｏｎ 方程的薄膜ＳＯＩ降低表面电场（ＲＥＳＵＲＦ结构解析物理模型．并在该模型基础上，给出了一种分析薄膜ＳＯＩＲＥＳＵＲＦ结构击穿电压的方法．利用这一方法计算了漂移区长度较长的薄膜ＳＯＩＲＥＳＵＲＦ结构击穿电压与漂移区掺杂浓度的关系，并定量分析了场ＳｉＯ２ 界面电荷密度对击穿电压和漂移区临界掺杂浓度的影响．首次提出了临界场ＳｉＯ２界面电荷密度的概念，并研究了其与漂移区掺杂浓度的关系．而且计算结果与ＭＥＤＩＣＩ模拟结果符合得很好．

均匀、阶梯和线性掺杂漂移区SOI RESURF器件的统一击穿模型(英文)

提出了一个均匀、阶梯和线性掺杂漂移区SOI高压器件的统一击穿模型 .基于分区求解二维Poisson方程 ,得到了不同漂移区杂质分布的横向电场和击穿电压的统一解析表达式 .借此模型并对阶梯数从 0到无穷时器件结构参数对临界电场和击穿电压的影响进行了深入研究 .从理论上揭示了在厚膜SOI器件中用阶梯掺杂取代线性漂移区 ,不但可以保持较高的耐压 ,而且降低了设计和工艺难度 .解析结果。

TFSOI RESURF功率器件表面电场分布和优化设计的新解析模型(英文)

提出了 TFSOI RESURF功率器件的表面电场分布和优化设计的新解析模型 .根据二维泊松方程的求解 ,得到了表面电场和电势分布的相关解析表达式 .在此基础上 ,推出了为获得最大击穿电压的优化条件。讨论了击穿电压和漂移区长度及临界掺杂浓度和场氧化层、埋氧化层的关系 .解析结果与半导体器件数值分析工具 DESSISE-ISE得到的数值分析基本一致 ,证明了新解析模型的适用性 .

具有多阶场板的300V薄层SOI RESURF nLDMOS设计

提出了一种具有多阶场板的300V薄层SOI RESURF nLDMOS器件。借助RESURF和MFP技术,优化了器件表面电场分布,避免了器件在表面提前击穿,提高了器件耐压。通过分析器件的结构参数,进一步得到优化的器件击穿电压和比导通电阻。与常规nLDMOS结构相比,该器件不仅具有高的击穿电压,而且制造工艺简单、成本低。

适于薄膜SOI RESURF器件击穿电压模拟的高阶紧致差分格式离散的ADI方法

采用ADI与高阶紧致差分相结合的方法计算薄膜SOI RESURF结构击穿电压.数值计算表明,这种方法可以降低方程的迭代次数约40%,并明显减少方程的求解时间.

SOI RESURF器件高压互连线效应的二维解析模型

高压互连线效应是影响集成功率器件性能的重要因素之一。首先提出一个高压互连线效应对SOI横向高压器件的漂移区电势和电场分布影响的二维解析模型,进而得到漂移区在不完全耗尽和完全耗尽情况下的器件击穿电压解析表达式,而后利用所建立的模型,研究器件结构参数对击穿特性的影响规律,定量揭示在高压互连线作用下器件击穿多生在阳极PN结的物理本质,指出通过优化场氧厚度可以弱化高压互连线对器件击穿的负面影响,并给出用于指导设计的理论公式。模型的正确性通过半导体二维器件仿真软件MEDICI进行了验证。

阶梯变掺杂漂移区高压SOI RESURF结构耐压机理研究

研究了阶梯变掺杂漂移区高压SOI RESURF(Reduce SURface Field)结构的器件几何形状和物理参数对器件耐压的影响;发现并解释了该结构纵向击穿时,耐压与浓度关系中特有的“多RESURF平台”现象。研究表明,阶梯变掺杂漂移区结构能明显改善表面电场分布,提高耐压,降低导通电阻,增大工艺容差;利用少数分区,能得到接近线性变掺杂的耐压,降低了工艺难度。

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

SOI高压LDMOS器件氧化层抗总电离剂量辐射效应研究

绝缘体上硅(SOI)高压横向扩散金属氧化物半导体(LDMOS)器件是高压集成电路的核心器件,对其进行了总电离剂量(TID)辐射效应研究。利用仿真软件研究了器件栅氧化层、场氧化层和埋氧化层辐射陷阱电荷对电场和载流子分布的调制作用,栅氧化层辐射陷阱电荷主要作用于器件沟道区,而场氧化层和埋氧化层辐射陷阱电荷则主要作用于器件漂移区;辐射陷阱电荷在器件内部感生出的镜像电荷改变了器件原有的电场和载流子分布,从而导致器件阈值电压、击穿电压和导通电阻等参数的退化。对80 V SOI高压LDMOS器件进行了总电离剂量辐射实验,结果表明在ON态和OFF态下随着辐射剂量的增加器件性能逐步衰退,当累积辐射剂量为200 krad(Si)时,器件的击穿电压大于80 V,阈值电压漂移为0.3 V,器件抗总电离剂量辐射能力大于200 krad(Si)。

SOI基双级RESURF二维解析模型

提出了SOI基双级RESURF二维解析模型.基于二维Poisson方程,获得了表面电势和电场分布解析表达式,给出了SOI的双级和单级RESURF条件统一判据,得到RESURF浓度优化区(DOR,dopingoptimalregion),研究表明该判据和DOR还可用于其他单层或双层漂移区结构.根据此模型,对双级RESURF结构的降场机理和击穿特性进行了研究,并利用二维器件仿真器MEDICI进行了数值仿真.以此为指导成功研制了耐压为560V和720V的双级RESURF高压SOILDMOS.解析解、数值解和实验结果吻合得较好.

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_（sp） is reduced from 16.5 to 13.8 mΩ·cm^2 in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV^2/R_（on）.It reduces R_（sp） by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.

A new analytical model of high voltage silicon on insulator(SOI) thin film devices

A new analytical model of high voltage silicon on insulator （SOI） thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage （VB,V） are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI （PSOI） high voltage device structure called a CI PSOI （charge island PSOI） is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n＋-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n＋-regions on the interface by the force with ionized donors in the undepleted n＋-regions, and therefore effectively enhance the electric field of the dielectric buried layer （Ei） and increase the breakdown voltage （BV）, thereby alleviating the self-heating effect （SHE） by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and El of the CI PSOI LDMOS increase to 631 V and 584 V/μm from 246 V and 85.8 V/μm for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.

Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI （silion-on-insulator） （PSOI） high voltage P-channel LDMOS （lateral double-diffused metal-oxide semiconductor） with an interface hole islands （HI） layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field （Er） in the dielectric buried oxide layer （BOX） and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage （BV）. The values of E1 and BV of an HI PSOI with a 2-~m thick SOI layer over a 1-~tm thick buried layer are 580V/~m and -582 V, respectively, compared with 81.5 V/p.m and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect （SHE）. Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.

Experimental and theoretical study of an improved breakdown voltage SOI LDMOS with a reduced cell pitch

An improved breakdown voltage （BV） SOI power MOSFET with a reduced cell pitch is proposed and fabricated. Its breakdown characteristics are investigated numerically and experimentally. The MOSFET features dual trenches （DTMOS）, an oxide trench between the source and drain regions, and a trench gate extended to the buried oxide （BOX）. The proposed device has three merits. First, the oxide trench increases the electric field strength in the x-direction due to the lower permittivity of oxide （eox） than that of Si （esi）. Furthermore, the trench gate, the oxide trench, and the BOX cause multi-directional depletion, improving the electric field distribution and enhancing the RESURF （reduced surface field） effect. Both increase the BV. Second, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Third, the trench gate not only reduces the on-resistance, but also acts as a field plate to improve the BV. Additionally, the trench gate achieves the isolation between high-voltage devices and the low voltage CMOS devices in a high-voltage integrated circuit （HVIC）, effectively saving the chip area and simplifying the isolation process. An 180 V prototype DTMOS with its applied drive IC is fabricated to verify the mechanism.

A charge allocating model for the breakdown voltage calculation and optimization of the lateral RESURF devices

A new quite simple analytical model based on the charge allocating approach has been proposed to describe the breakdown property of the RESURF （reduced surface field） structure. It agrees well with the results of numerical simulation on predicting the breakdown voltage. Compared with the latest published analytical model, this model has a better accuracy according to the numerical simulation with simpler form. The optimal doping concentration （per unit area） of the epi-layer of the RESURF structures with different structure parameters has been calculated based on this model and the results show no significant discrepancy to the data gained by others. Additionally the physical mechanism of how the surface field is reduced is clearly illustrated by this model.

阶梯分布埋氧层固定电荷SOI高压器件新结构和耐压模型

提出了具有阶梯分布埋氧层固定电荷 (SBOC) SOI新型高压器件 ,并借助求解多区二维泊松方程建立其击穿电压模型 ,对阶梯数 n从 0到∞时的器件击穿特性进行了研究 .结果表明 ,该结构突破常规 SOI结构纵向耐压极限 ,使埋氧层电场从常规 75 V/μm提高到 5 0 0 V/μm以上 ;同时得到均匀的表面电场分布 ,缓解了器件尺寸和击穿电压之间的矛盾 ,因此 SBOC结构是一种改善 SOI耐压的良好结构 .

阶梯掺杂漂移区SOI高压器件浓度分布优化模型

基于分区求解二维泊松方程,提出了阶梯掺杂漂移区SOI高压器件的浓度分布优化模型。借助此模型,对阶梯数从0到无穷时SOIRESURF结构的临界电场和击穿电压进行了研究。结果表明,对于所研究的结构,一阶或二阶掺杂可以在不提高工艺难度的情况下获得足够高的击穿电压,因而可以作为线性漂移区的理想近似。解析结果、MEDICI仿真结果和实验结果非常吻合,证明了模型的正确性。