The hot-carrier-induced oxide breakdown i s systematically clarified for partially depleted SOI NMOSFET's fabricated on SI MOX wafer.The gate oxide properties are considered to analyze the channel hot-c arrier eff...The hot-carrier-induced oxide breakdown i s systematically clarified for partially depleted SOI NMOSFET's fabricated on SI MOX wafer.The gate oxide properties are considered to analyze the channel hot-c arrier effects.Hot-carrier-induced device degradations are also analyzed by st ress experiments under three typical hot-carrier injection conditions.Based on these results,the influence of channel hot carriers on SOI NMOSFET's front-chan nel properties is investigated.A power time dependence extrapolation technique i s proposed to predict the device's lifetime.Experimental results show that the N MOSFET's degradation is caused by the hot-holes,which are injected into the gat e oxide from the drain and then trapped near the drain side.However,the electron s trapped in the gate oxide can accelerate the gate breakdown.The two simultaneo us breakages of Si-O bonds at a Si atom lead to the irreversible relaxation of the oxide network.A novel physical mechanism of channel hot-carrier-induced ga te oxide breakdown is also presented.展开更多
DSOI,bulk Si and SOI MOSFETs are fabricated on the same die successfully using local oxygen implantation process.The thermal properties of the three kinds of devices are described and compared from simulation and mea...DSOI,bulk Si and SOI MOSFETs are fabricated on the same die successfully using local oxygen implantation process.The thermal properties of the three kinds of devices are described and compared from simulation and measurement.Both simulation and measurement prove that DSOI MOSFETs have the advantage of much lower thermal resistance of substrate and suffer less severe self heating effect than their SOI counterparts. At the same time,the electrical advantages of SOI devices can stay.The thermal resistance of DSOI devices is very close to that of bulk devices and DSOI devices can keep this advantage into deep sub micron realm.展开更多
The forward gated-diode R-G current method is used to monitor the F-N stressing-induced interface traps of NMOSFET/SOI.This simp le and accurate experiment method can directly give the interface trap density i nduced...The forward gated-diode R-G current method is used to monitor the F-N stressing-induced interface traps of NMOSFET/SOI.This simp le and accurate experiment method can directly give the interface trap density i nduced by F-N stressing effect for characterizing the device's reliability.For the measured NMOS/SOI device with a body structure,an expected power-law relati onship as Δ N it - t 0 4 between the pure F-N stressing-indu ced interface trap density and the accumulated stressing time is obtained.展开更多
A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with ...A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.展开更多
A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface pote...A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.展开更多
文摘The hot-carrier-induced oxide breakdown i s systematically clarified for partially depleted SOI NMOSFET's fabricated on SI MOX wafer.The gate oxide properties are considered to analyze the channel hot-c arrier effects.Hot-carrier-induced device degradations are also analyzed by st ress experiments under three typical hot-carrier injection conditions.Based on these results,the influence of channel hot carriers on SOI NMOSFET's front-chan nel properties is investigated.A power time dependence extrapolation technique i s proposed to predict the device's lifetime.Experimental results show that the N MOSFET's degradation is caused by the hot-holes,which are injected into the gat e oxide from the drain and then trapped near the drain side.However,the electron s trapped in the gate oxide can accelerate the gate breakdown.The two simultaneo us breakages of Si-O bonds at a Si atom lead to the irreversible relaxation of the oxide network.A novel physical mechanism of channel hot-carrier-induced ga te oxide breakdown is also presented.
文摘DSOI,bulk Si and SOI MOSFETs are fabricated on the same die successfully using local oxygen implantation process.The thermal properties of the three kinds of devices are described and compared from simulation and measurement.Both simulation and measurement prove that DSOI MOSFETs have the advantage of much lower thermal resistance of substrate and suffer less severe self heating effect than their SOI counterparts. At the same time,the electrical advantages of SOI devices can stay.The thermal resistance of DSOI devices is very close to that of bulk devices and DSOI devices can keep this advantage into deep sub micron realm.
文摘The forward gated-diode R-G current method is used to monitor the F-N stressing-induced interface traps of NMOSFET/SOI.This simp le and accurate experiment method can directly give the interface trap density i nduced by F-N stressing effect for characterizing the device's reliability.For the measured NMOS/SOI device with a body structure,an expected power-law relati onship as Δ N it - t 0 4 between the pure F-N stressing-indu ced interface trap density and the accumulated stressing time is obtained.
基金Project 60472003 supported by National Natural Science Foundation of China and 2005CB321701 by the State Key Development Program for BasicResearch of China
文摘A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.
文摘A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.
