CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
软锁相环(Soft Phase-locked Loop,SPLL)在现代工业控制尤其是电网电压相位锁定中得到越来越多的应用。分析了SPLL的基本结构和工作原理,针对传统SPLL运算量大、不利于在数字处理器(Digital Signal Processor,DSP)上实现的缺点,设计了...软锁相环(Soft Phase-locked Loop,SPLL)在现代工业控制尤其是电网电压相位锁定中得到越来越多的应用。分析了SPLL的基本结构和工作原理,针对传统SPLL运算量大、不利于在数字处理器(Digital Signal Processor,DSP)上实现的缺点,设计了一种改进型电网电压SPLL。根据电网电压SPLL工作原理,结合坐标变换关系,从结果出发,通过相角已锁定的性质来做逆向思考简化控制算法。动态计算SPLL的PI参数,以使锁相功能动态响应更好、控制算法运算量更少。理论分析、仿真研究都表明改进后的SPLL算法简单,动态响应快,能够抑制电网电压三相不平衡及谐波干扰,能够应对电网突然掉电等故障,非常利于在DSP中实现。展开更多
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
文摘软锁相环(Soft Phase-locked Loop,SPLL)在现代工业控制尤其是电网电压相位锁定中得到越来越多的应用。分析了SPLL的基本结构和工作原理,针对传统SPLL运算量大、不利于在数字处理器(Digital Signal Processor,DSP)上实现的缺点,设计了一种改进型电网电压SPLL。根据电网电压SPLL工作原理,结合坐标变换关系,从结果出发,通过相角已锁定的性质来做逆向思考简化控制算法。动态计算SPLL的PI参数,以使锁相功能动态响应更好、控制算法运算量更少。理论分析、仿真研究都表明改进后的SPLL算法简单,动态响应快,能够抑制电网电压三相不平衡及谐波干扰,能够应对电网突然掉电等故障,非常利于在DSP中实现。
