提出了基于写优先FIFO(First In First Out,先进先出)结构的SRAM缓存法,解决了线阵CCD(Charge Coupled Device,电荷耦合元件)大幅面扫描仪USB(Universal Serial Bus,通用串行总线)传输中图像失真的难题,制作了国内第一台高速线阵CCD大...提出了基于写优先FIFO(First In First Out,先进先出)结构的SRAM缓存法,解决了线阵CCD(Charge Coupled Device,电荷耦合元件)大幅面扫描仪USB(Universal Serial Bus,通用串行总线)传输中图像失真的难题,制作了国内第一台高速线阵CCD大幅面扫描仪。该方法的基本原理是通过在USB传输模块前端增加大缓存,保证USB传输间歇期间,来自线阵CCD传感器的数据被全部保存。实验结果证明,改进后的线阵CCD大幅面扫描仪工作在600 DPI分辨率,1 200 Hz行频,USB传输速度达到256 Mbit/s时,未出现图像失真。据我们所知,该改进方法,国内、外文献未见报道。展开更多
This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit...This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process.Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.展开更多
文摘提出了基于写优先FIFO(First In First Out,先进先出)结构的SRAM缓存法,解决了线阵CCD(Charge Coupled Device,电荷耦合元件)大幅面扫描仪USB(Universal Serial Bus,通用串行总线)传输中图像失真的难题,制作了国内第一台高速线阵CCD大幅面扫描仪。该方法的基本原理是通过在USB传输模块前端增加大缓存,保证USB传输间歇期间,来自线阵CCD传感器的数据被全部保存。实验结果证明,改进后的线阵CCD大幅面扫描仪工作在600 DPI分辨率,1 200 Hz行频,USB传输速度达到256 Mbit/s时,未出现图像失真。据我们所知,该改进方法,国内、外文献未见报道。
基金supported by the MOST(Grant Nos.2010CB934200 and 2011CBA00600)the National Natural Science Foundation of China(Grant Nos.61176073 and 61221004)
文摘This paper presents an embedded SRAM design for write buffer applications in flash memories.The write buffer is implemented with a newly proposed self-adaptive timing control circuit,an area-saving sense-latch circuit and 6 T SRAM cell units.A 2 kb SRAM macro with the area of 135μm×180μm is implemented in and applied to a 128 Mb NOR flash memory with the SMIC 65 nm NOR flash memory process.Both simulation and chip test results show that the SRAM write buffer is beneficial to high-density flash memory design.
