A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA)

In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method.

Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA)

An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems.

Novel Test Approach for Interconnect Resources in Field Programmable Gate Arrays

A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.

一款基于新型Field Programmable Gate Array芯片的投影仪梯形校正系统研究与实现

投影设备配备的梯形校正普遍存在校正范围小,画面的一些线条和字符边缘会出现毛刺和不平滑现象,矫正效果不理想.如果采用通用的图像处理芯片和复杂的算法,可以解决上述问题,但又会导致成本急剧上升.为了解决上述矛盾,提出一种基于FPGA(Field Programmable Gate Array)芯片的新型梯形校正实现方案,解决了校正范围与锯齿失真的矛盾问题,并为进一步成为芯片级产品铺平了道路.图像处理采用kaiser窗函数和sinc函数相结合的方法进行插值,这样的滤波器改善了旁瓣抑制,具有较好的通带性能.介绍了梯形失真的产生和校正原理,提出了利用FPGA芯片XC3S400作为核心图像处理单元的梯形校正系统的硬件和软件实现,说明了该芯片结构、功能及特性,最后提供了校正的效果图.

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA’s Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable.

Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software

In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment.

FPGA-Based Efficient Programmable Polyphase FIR Filter

The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)

Low complexity SEU mitigation technique for SRAM-based FPGAs

An internal single event upset（SEU）mitigation technique is proposed,which reads back the configuration frames from the static random access memory（SRAM）-based field programmable gate array（FPGA）through an internal port and compares them with those stored in the radiationhardened memory to detect and correct SEUs.Triple modular redundancy（TMR）,which triplicates the circuit of the technique and uses majority voters to isolate any single upset within it,is used to enhance the reliability.Performance analysis shows that the proposed technique can satisfy the requirement of ordinary aerospace missions with less power dissipation,size and weight.The fault injection experiment validates that the proposed technique is capable of correcting most errors to protect spaceborne facilities from SEUs.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

An alternative approach of the programmable arrays and applications

There is an increasing interest of using the Programmable arrays for performing different hardware. In this paper we give an alternative approach and the applications of the Programmable Gate Arrays. We show the field and the domain where they are more adequate and wihch kind of Programmable array is more efficient to apply. The DPGA and the FPGA are both Programmable Gate Array. They have more possibilities then the conventional devices such as 64 bits microprocessor, however a microprocessor coupled with a programmable array has more opportunity and their implementation is increasing. It is impossible to enumerate all possible uses of Programmable Gate Array. However we use the parameters Latency and throughput. Finite State Machine(FSM), control of data path, processor coupled with a programmable array to build up an alternative approach of the devices and their applications.

Implimentations of SIMD machine using programmable gate array

Field Programmable Gate Array(FPGA) and Single Instruction Multiple Data(SIMD) processing array share many architecture features. In both architectures, an array is employed to provide high speed computation. In this paper we show that the implementation of a Single Instruction Multiple Data (SIMD) machine the ABC 90 using the Field Programmable Gate Array (FPGA) is not completely suitable because of its characteristics. The comparison between the programmable gate arrays show that, they have many architectures features in common. Within this framework, we examine the differences and similarities between these array structures and touch upon techniques and lessons which can be done between these architectures in order to choose the appropriate Programmable gate array to implement a general purpose parallel computer. In this paper we introduce the principal of the Dynamically Programmable Date Array(DPGA) which combines the best feature of the FPGA and the SIMD arrays into a single array architecture. By the same way we show that the DPGA is more appropriate then the FPGA for wiring, hardwiring the general purpose parallel computers: SIMD and its implementation.

基于FPGA的新能源低压直流配电系统暂态实时仿真研究

对新能源低压直流配电系统开展暂态实时仿真研究对优化其运行控制具有重要作用。由于现场可编程门阵列(FPGA)内部集成了大量具有不同功能的电路,FPGA正成为电力系统暂态实时仿真领域主要的计算载体之一。该文面向新能源低压直流配电系统的暂态实时仿真需求,开发了一种基于FPGA的包含小型分布式风力发电、光伏发电以及蓄电池储能单元的新能源低压直流配电系统暂态实时仿真器。首先,研究构建了分布式发电单元和典型控制回路的计算模块,利用FPGA的并行计算特性并结合“算法-结构-有效匹配(AAA)”理念建立了底层模块串并联混合求解结构;然后,在节点分析法的框架下,建立了一种结合矩阵LDU分解和有向无环图(DAG)的电气系统节点电导矩阵并行求解方法;最后,在建立电气系统与控制系统并行求解架构的基础上,开发了一种基于FPGA的新能源低压直流配电系统暂态实时仿真器,通过将其仿真结果与PSCAD/EMTDC离线仿真平台的计算结果进行对比,验证了所开发暂态实时仿真器的有效性和准确性。

基于FPGA的PMLSM三矢量模型预测电流控制IP核设计及硬件在环验证

为了提升永磁直线同步电机(PMLSM)电流控制的稳态性能和执行速度,同时降低资源消耗,基于现场可编程门阵列(FPGA)设计了一个三矢量模型预测电流控制(TV-MPCC)知识产权(IP)核,并利用FPGA在环可视化验证方法,建立了一个PMLSM的TV-MPCC IP核验证系统。通过Simulink对TV-MPCC策略进行算法级仿真,并优化了基本电压矢量的作用顺序;采用并行与资源共享硬件优化技术设计并封装了一个TV-MPCC IP核,并对其进行了功能仿真;将设计部署在FPGA芯片XC7Z020CLG400-2上,利用FPGA在环可视化验证平台进行实验研究。结果表明,TV-MPCC策略下d、q轴电流跟踪误差和电流脉动均降低90%以上;FPGA工作在100 MHz下,实现一次算法的时间为0.62μs,仅为软件PyCharm执行时间的0.414%。

一种基于FPGA的FTN-VLC系统设计与测试

为了提升可见光通信(VLC)系统的传输速率和频谱利用率,设计了一种基于现场可编程门阵列(FPGA)超奈奎斯特(FTN)-VLC系统。该系统主要由FPGA、数/模(D/A)转换器、低通滤波器、雪崩二极管、电流/电压(I/V)转换器和电压比较器组成。对系统的软件和硬件进行了仿真分析和性能测试。仿真与测试结果表明:当传输距离为0.5 m时,系统的数据传输速率可达10 Mb/s,频谱利用率较同等条件下的奈奎斯特光通信系统提升了18.25%。

应答器上行链路信号自适应解调方法的FPGA实现

为降低电磁干扰对信号传输的影响,分析了应答器上行链路信号传输过程及其易遭受干扰信号的特点,设计了基于符号最小均方误差(least mean square,LMS)算法的自适应解调方法。为在硬件平台中实现该解调方法,通过仿真计算,确定LMS算法的自适应算法中间变量变化范围,使用截位操作完成权值系数的更新,设置均衡器长度、步长因子、中值滤波系数分别为1、1/64、16,可在不占用过多硬件资源情况下获得良好的解调性能。解调算法在现场可编程门阵列(field programmable gata array,FPGA)上予以验证,实验表明,当信噪比为6 dB时,FPGA中自适应解调误码率为0.000001,在信噪比大于等于6 dB时,实测误码率与仿真分析误码率基本一致;FPGA自适应解调方法在列车不同速度等级下误码率均小于10^(-6)。

基于FPGA的小信号高精度采集系统设计

针对激光打靶实验中对靶心温度和光照强度的高精度采集需求,以现场可编程门阵列(FPGA)为核心,实现了一种多路高精度采集系统。系统通过对信号源输出的模拟K型热电偶的信号进行采集,将采集的信号作为样本,估计出每个通道的增益误差和偏移量,借助最小二乘法得到每个通道修正误差所需要的系数,最后再通过配置AD7768实现对误差的修正。实验结果表明:在修正前增益误差为0.207 8%,修正之后增益误差为0.002 7%,采用修正方法后,实现采集误差在10μV以内,有效地提高了系统对微小信号的采集精度。

数字示波器中FPGA间高速信号传输同步方法

数据采集系统是数字示波器(DSO)的核心组成单元,随着示波器带宽采样率的逐步提升,单片模数转换器(ADC)+现场可编辑门控阵列(FPGA)的架构难以满足超高速以及多通道的应用场景,因此,高端示波器中数据采集系统普遍采用“主从”FPGA控制架构。在该架构下,多个FPGA之间信号的同步传输是实现采集系统的同步和精确采集的重要前提。针对多FPGA板卡之间的信号同步传输问题,提出了一种FPGA之间高速信号同步传输的方法,借助FPGA的IODELAY单元,通过测试数据训练找到最稳定的同步传输区间,实现多FPGA之间的同步传输。在自研的数字示波器上的实验表明,该方法能够有效实现FPGA之间高速信号的同步传输。

基于FPGA的两阶段配电网拓扑实时辨识算法

对配电网拓扑进行准确的实时辨识是电力系统安全稳定运行的基础,但随着新能源的接入以及配电网规模不断增大,配电网拓扑结构的动态变化愈加频繁且难以辨识。然而,现有配电网拓扑辨识算法所使用的历史数据需要人工对其进行拓扑标注,且拓扑辨识时间长,难以实现配电网拓扑实时辨识。因此,文中提出了一种基于现场可编程逻辑门阵列(FPAG)的两阶段配电网拓扑结构实时辨识算法。该算法不需要预先给出配电网拓扑类别的数量,即可对已有历史数据进行相应的拓扑标注及分类,并且基于FPGA实现了对配电网拓扑的实时辨别。该算法分为2个阶段:第1阶段采用变分贝叶斯高斯混合模型,对已有历史数据进行相应的拓扑标注及分类;第2阶段采用麻雀搜索算法,使得支持向量机快速收敛得到最优参数,以实现对配电网拓扑结构的精准辨识。基于该算法,利用FPGA并行架构以及高速高密度特性建立了实时拓扑结构辨识平台。最后,通过算例分析验证了所提辨识方法的有效性和优越性。

基于FPGA的磁量热计数据采集系统研制

磁量热计是基于量热法的低温粒子探测器,可实现射线高分辨测量。为解决磁量热信号微弱易受到噪声影响导致信号采集困难的难题,本研究基于现场可编程门阵列(FPGA)研发了一套磁量热计数据采集系统,并对搭建的系统进行测试,成功实现了^(60)Co能谱数据和磁量热信号噪声谱的采集,且能谱展宽与信号放大倍数之间的线性拟合R2达到0.978 1,表明该系统可有效实现信号采集。在离线模式下使用梯形滤波、平顶尖峰滤波、高斯滤波对传统核探测器信号、模拟及实际的磁量热信号分别进行成形效果及能量分辨力优化效果的对比,三者中平顶尖峰滤波性能最优越,可以使高纯锗对^(241)Am源59.54 keV的γ能量分辨力从0.598 keV提高到0.536 keV,验证了数字滤波的必要性,可为磁量热计数字滤波方法选择提供可靠依据。

基于FPGA的卷积神经网络和视觉Transformer通用加速器

针对计算机视觉领域中基于现场可编程逻辑门阵列(FPGA)的传统卷积神经网(CNN)络加速器不适配视觉Transformer网络的问题,该文提出一种面向卷积神经网络和Transformer的通用FPGA加速器。首先,根据卷积和注意力机制的计算特征,提出一种面向FPGA的通用计算映射方法;其次,提出一种非线性与归一化加速单元,为计算机视觉神经网络模型中的多种非线性和归一化操作提供加速支持;然后,在Xilinx XCVU37P FPGA上实现了加速器设计。实验结果表明,所提出的非线性与归一化加速单元在提高吞吐量的同时仅造成很小的精度损失,ResNet-50和ViT-B/16在所提FPGA加速器上的性能分别达到了589.94 GOPS和564.76 GOPS。与GPU实现相比,能效比分别提高了5.19倍和7.17倍;与其他基于FPGA的大规模加速器设计相比,能效比有明显提高,同时计算效率较对比FPGA加速器提高了8.02%~177.53%。