The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature f...The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature from -55 to 125℃ and independent of radiation up to 1×10^6rad（Si） for the supply voltage VDD.The standby current is 0.65μA before the total dose of radiation and is only 0.80mA after radiation exposure,which is much better than the specified 10mA.The operating power supply current is 33.0mA before and only 38.1mA afterward,which is much better than the specified 100mA.展开更多
We report on the temperature dependence of single-event upsets in the 215–353 K range in a 4M commercial SRAM manufactured in a 0.15-lm CMOS process,utilizing thin film transistors. The experimental results show that...We report on the temperature dependence of single-event upsets in the 215–353 K range in a 4M commercial SRAM manufactured in a 0.15-lm CMOS process,utilizing thin film transistors. The experimental results show that temperature influences the SEU cross section on the rising portion of the cross-sectional curve(such as the chlorine ion incident). SEU cross section increases 257 %when the temperature increases from 215 to 353 K. One of the possible reasons for this is that it is due to the variation in upset voltage induced by changing temperature.展开更多
Single event upsets(SEUs) induced by heavy ions were observed in 65 nm SRAMs to quantitatively evaluate the applicability and effectiveness of single-bit error correcting code(ECC) utilizing Hamming Code.The results s...Single event upsets(SEUs) induced by heavy ions were observed in 65 nm SRAMs to quantitatively evaluate the applicability and effectiveness of single-bit error correcting code(ECC) utilizing Hamming Code.The results show that the ECC did improve the performance dramatically,with the SEU cross sections of SRAMs with ECC being at the order of 10^(-11) cm^2/bit,two orders of magnitude higher than that without ECC(at the order of 10^(-9) cm^2/bit).Also,ineffectiveness of ECC module,including 1-,2- and 3-bits errors in single word(not Multiple Bit Upsets),was detected.The ECC modules in SRAMs utilizing(12,8) Hamming code would lose work when 2-bits upset accumulates in one codeword.Finally,the probabilities of failure modes involving 1-,2- and 3-bits errors,were calcaulated at 39.39%,37.88%and 22.73%,respectively,which agree well with the experimental results.展开更多
The single event effect(SEE),total ionizing dose(TID)e ect,and synergy between the TID and SEE in electronic devices have been extensively studied.Schwank,et al.,have irradiated many kinds of static random access memo...The single event effect(SEE),total ionizing dose(TID)e ect,and synergy between the TID and SEE in electronic devices have been extensively studied.Schwank,et al.,have irradiated many kinds of static random access memory(SRAM)devices with various radiation sources,such as-ray,X-ray,and proton,and then measured the single event upset(SEU)cross-section of the devices.展开更多
We report on irradiation induced single event upset（SEU） by high-energy protons and heavy ions. The experiments were performed at the Paul Scherer Institute, and heavy ions at the SEE irradiating Facility on the HI-...We report on irradiation induced single event upset（SEU） by high-energy protons and heavy ions. The experiments were performed at the Paul Scherer Institute, and heavy ions at the SEE irradiating Facility on the HI-13 Tandem Accelerator in China＇s Institute of Atomic Energy, Beijing and the Heavy Ion Research Facility in Lanzhou in the Institute of Modern Physics, Chinese Academy of Sciences. The results of proton and heavy ions induced（SEU） in 65 nm bulk silicon CMOS SRAMS are discussed and the prediction on several typical orbits are presented.展开更多
The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area o...The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.展开更多
More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These tran...More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These transistors offer advantages such as high carrier mobility,large saturation velocity,low intrinsic capacitance,flexibility,and transparency.The three-dimensional multilayer structure of the CNTFET semiconductor chip,along with ongoing research in CNTFET manufacturing processes,increases the potential for creating a hybrid MOSFET-CNTFET semiconductor chip.This chip combines conventional metal-oxide-semiconductor field-effect transistors(MOSFETs)and CNTFETs in one integrated system.This paper discusses a methodology to design 6T binary static random-access memory(SRAM)using a hybrid MOSFET-CNTFET.This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAM by leveraging existing MOSFET SRAM or CNTFET SRAM design approaches.Additionally,this paper compares its performance with conventional MOSFET SRAM and CNTFET SRAM designs.展开更多
文摘The first domestic 1×10^6rad（Si） total dose hardened 1.2μm partially depleted silicon-on-insulator （PDSOI） 64k SRAM fabricated in SIMOX is demonstrated.The address access time is independent of temperature from -55 to 125℃ and independent of radiation up to 1×10^6rad（Si） for the supply voltage VDD.The standby current is 0.65μA before the total dose of radiation and is only 0.80mA after radiation exposure,which is much better than the specified 10mA.The operating power supply current is 33.0mA before and only 38.1mA afterward,which is much better than the specified 100mA.
基金the National Natural Science Foundation of China(No.11405275)
文摘We report on the temperature dependence of single-event upsets in the 215–353 K range in a 4M commercial SRAM manufactured in a 0.15-lm CMOS process,utilizing thin film transistors. The experimental results show that temperature influences the SEU cross section on the rising portion of the cross-sectional curve(such as the chlorine ion incident). SEU cross section increases 257 %when the temperature increases from 215 to 353 K. One of the possible reasons for this is that it is due to the variation in upset voltage induced by changing temperature.
基金Supported by the National Natural Science Foundation of China(Nos.11079045 and 11179003)the Important Direction Project of the CAS Knowledge Innovation Program(No.KJCX2-YW-N27)
文摘Single event upsets(SEUs) induced by heavy ions were observed in 65 nm SRAMs to quantitatively evaluate the applicability and effectiveness of single-bit error correcting code(ECC) utilizing Hamming Code.The results show that the ECC did improve the performance dramatically,with the SEU cross sections of SRAMs with ECC being at the order of 10^(-11) cm^2/bit,two orders of magnitude higher than that without ECC(at the order of 10^(-9) cm^2/bit).Also,ineffectiveness of ECC module,including 1-,2- and 3-bits errors in single word(not Multiple Bit Upsets),was detected.The ECC modules in SRAMs utilizing(12,8) Hamming code would lose work when 2-bits upset accumulates in one codeword.Finally,the probabilities of failure modes involving 1-,2- and 3-bits errors,were calcaulated at 39.39%,37.88%and 22.73%,respectively,which agree well with the experimental results.
基金National Natural Science Foundation of China(12105341,12035019)。
文摘The single event effect(SEE),total ionizing dose(TID)e ect,and synergy between the TID and SEE in electronic devices have been extensively studied.Schwank,et al.,have irradiated many kinds of static random access memory(SRAM)devices with various radiation sources,such as-ray,X-ray,and proton,and then measured the single event upset(SEU)cross-section of the devices.
文摘We report on irradiation induced single event upset（SEU） by high-energy protons and heavy ions. The experiments were performed at the Paul Scherer Institute, and heavy ions at the SEE irradiating Facility on the HI-13 Tandem Accelerator in China＇s Institute of Atomic Energy, Beijing and the Heavy Ion Research Facility in Lanzhou in the Institute of Modern Physics, Chinese Academy of Sciences. The results of proton and heavy ions induced（SEU） in 65 nm bulk silicon CMOS SRAMS are discussed and the prediction on several typical orbits are presented.
基金supported by the National Natural Science Foundation of China(Nos.12105341 and 12035019)the opening fund of Key Laboratory of Silicon Device and Technology,Chinese Academy of Sciences(No.KLSDTJJ2022-3).
文摘The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.
基金supported by Seokyeong University in 2022.The EDA tool was supported by the IC Design Education Center(IDEC),Korea.
文摘More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These transistors offer advantages such as high carrier mobility,large saturation velocity,low intrinsic capacitance,flexibility,and transparency.The three-dimensional multilayer structure of the CNTFET semiconductor chip,along with ongoing research in CNTFET manufacturing processes,increases the potential for creating a hybrid MOSFET-CNTFET semiconductor chip.This chip combines conventional metal-oxide-semiconductor field-effect transistors(MOSFETs)and CNTFETs in one integrated system.This paper discusses a methodology to design 6T binary static random-access memory(SRAM)using a hybrid MOSFET-CNTFET.This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAM by leveraging existing MOSFET SRAM or CNTFET SRAM design approaches.Additionally,this paper compares its performance with conventional MOSFET SRAM and CNTFET SRAM designs.
