Single-event effects induced by medium-energy protons in 28 nm system-on-chip

Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed.

Investigation of single event effect in 28-nm system-on-chip with multi patterns

Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case.

A 130-nm ferroelectric nonvolatile system-on-chip for internet of things

IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation progress over power outages.Recently.

Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware

Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms.

Data Fusion with Genetic Algorithm Based Lifetime Prediction for Dependable Multi-Processor System-on-Chips

With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread use of MP-SoCs can lead to an undesirable decrease in their dependability.This study presents a promising approach using a group of Embedded Instruments(EIs)inside a processor core for health monitoring.Multiple health monitoring datasets obtained from the employed EIs are sampled and collated via the implemented experiment and thereafter used for conducting its remaining useful lifetime prognostics.This enables MP-SoCs to undertake preventive self-repair,thus realizing a zero mean downtime system and ensuring improved dependability.In addition,a principal component analysis based algorithm is designed for realizing the EI data fusion.Subsequently,a genetic algorithm based degradation optimization is employed to create a lifetime prediction model with respect to the processor.

Review on the Usage of Synchronous and Asynchronous FIFOs in Digital Systems Design

First-Input-First-Output (FIFO) buffers are extensively used in contemporary digital processors and System-on-Chips (SoC). There are synchronous FIFOs and asycnrhonous FIFOs. And different sized FIFOs should be implemented in different ways. FIFOs are used not only for the pipeline design within a processor, for the inter-processor communication networks, for example Network-on-Chips (NoCs), but also for the peripherals and the clock domain crossing at the whole SoC level. In this paper, we review the interface, the circuit implementation, and the various usages of FIFOs in various levels of the digital design. We can find that the usage of FIFOs could greatly facilitate the signal storage, signal decoupling, signal transfer, power domain separation and power domain crossing in digital systems. We hope that more attentions are paid to the usages of synchronous and asynchronous FIFOs and more sophististicated usages are discovered by the digital design communities.

IoT Based Smart Framework Monitoring System for Power Station

Power Station(PS)monitoring systems are becoming critical,ensuring electrical safety through early warning,and in the event of a PS fault,the power supply is quickly disconnected.Traditional technologies are based on relays and don’t have a way to capture and store user data when there is a problem.The proposed framework is designed with the goal of providing smart environments for protecting electrical types of equipment.This paper proposes an Internet of Things(IoT)-based Smart Framework(SF)for monitoring the Power Devices(PD)which are being used in power substations.A Real-Time Monitoring(RTM)system is proposed,and it uses a state-of-the-art smart IoT-based System on Chip(SoC)sensors,a Hybrid Prediction Model(HPM),and it is being used in Big Data Processing(BDP).The Cloud Server(CS)processes the data and does the data analytics by comparing it with the historical data already stored in the CS.No-Structural Query Language Mongo Data Base(MDB)is used to store Sensor Data(SD)from the PSs.The proposed HPM combines the Density-Based Spatial Clustering of Applications with Noise(DBSCAN)-algorithm for Outlier Detection(OD)and the Random Forest(RF)classification algorithm for removing the outlier SD and providing Fault Detection(FD)when the PD isn’t working.The suggested work is assessed and tested under various fault circumstances that happened in PSs.The simulation outcome proves that the proposed model is effective in monitoring the smooth functioning of the PS.Also,the suggested HPM has a higher Fault Prediction(FP)accuracy.This means that faults can be found earlier,early warning signals can be sent,and the power supply can be turned off quickly to ensure electrical safety.A powerful RTM and event warning system can also be built into the system before faults happen.

A Low-Power 12-Bit SAR ADC for Analog Convolutional Kernel of Mixed-Signal CNN Accelerator

As deep learning techniques such as Convolutional Neural Networks(CNNs)are widely adopted,the complexity of CNNs is rapidly increasing due to the growing demand for CNN accelerator system-on-chip(SoC).Although conventional CNN accelerators can reduce the computational time of learning and inference tasks,they tend to occupy large chip areas due to many multiply-and-accumulate(MAC)operators when implemented in complex digital circuits,incurring excessive power consumption.To overcome these drawbacks,this work implements an analog convolutional filter consisting of an analog multiply-and-accumulate arithmetic circuit along with an analog-to-digital converter(ADC).This paper introduces the architecture of an analog convolutional kernel comprised of low-power ultra-small circuits for neural network accelerator chips.ADC is an essential component of the analog convolutional kernel used to convert the analog convolutional result to digital values to be stored in memory.This work presents the implementation of a highly low-power and area-efficient 12-bit Successive Approximation Register(SAR)ADC.Unlink most other SAR-ADCs with differential structure;the proposed ADC employs a single-ended capacitor array to support the preceding single-ended max-pooling circuit along with minimal power consumption.The SARADCimplementation also introduces a unique circuit that reduces kick-back noise to increase performance.It was implemented in a test chip using a 55 nm CMOS process.It demonstrates that the proposed ADC reduces Kick-back noise by 40%and consequently improves the ADC’s resolution by about 10%while providing a near rail-to-rail dynamic rangewith significantly lower power consumption than conventional ADCs.The ADC test chip shows a chip size of 4600μm^(2)with a power consumption of 6.6μW while providing an signal-to-noise-and-distortion ratio(SNDR)of 68.45 dB,corresponding to an effective number of bits(ENOB)of 11.07 bits.

基于PLC的塑料挤出机远程监控系统设计

为了保证塑料挤出机稳定运行,提高企业生产效率,对生产设备进行远程监控,设计开发了基于可编程逻辑控制器(PLC)的塑料挤出机远程监控系统。该系统由数据采集模块与生产监控平台两部分构成。其中,数据采集模块主要以树莓派单片机为基础,从PLC中读取数据再发送到云服务器,生产监控平台可以远程对塑料挤出机的挤出量、电流、转速与机筒温度进行监控,记录设备保养信息,提供设备报警等功能。该塑料挤出机远程监控系统操作简单,实用性强,确保了挤出机的安全、稳定、高效运行。

基于触觉感知的自行车后视系统

为了在自行车转向或变道时,实现无需左右回头观察即可了解后方路况,设计了一套便于骑行者感知车后具体情况的自行车后视系统.该系统可分为车尾探测装置与终端反应手套,主要由USB摄像头与执行模块构成,并采用了you only look once(YOLO)v4目标检测算法.通过在自行车车尾安装检测设备,与骑手的特制手套进行无线通信,从而传递车后方探测到的有关安全状况的紧急信息.实验结果表明:该系统能够对后方的行进车辆进行多目标检测及警告优先级目标,并在足够的安全距离内识别率较高.

生化微传感SOC片内嵌入ADC的设计与实现

首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/-1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求.

安全通信协议设计及其芯片化实现

数据采集终端通过无线互联网与主站系统进行数据传输时会遇到安全问题,文章提出了一种安全解决方案,该方案设计了一套轻量级安全通信协议,采用可集成安全通信协议硬件安全芯片并将该安全通信协议集成到硬件安全芯片中。数据采集终端在使用了该硬件安全芯片后,只需要进行少量的软件改造即可实现与主站系统的安全数据传输;同时,硬件集成的方式能够有效防止安全通信协议扩散。实验结果表明,该方案完全满足安全通信的功能要求,而且性能更好。

基于SOC与触摸屏技术的硬笔书法练习设备的设计

在电子产品设计过程中要充分考虑系统自身特点,根据需要设计并解决各个功能模块。本课题依据系统在设计和使用中涉及的各种状态及数据,结合现代电子技术与数据处理技术,提出适合于该硬笔书法练习系统的解决方案,并基于硬件系统实现各模块的功能,证明了方案的正确性及可实现性。

三种SoC片上总线的分析与比较

随着以IP核复用为基础的SoC设计技术的发展,工业界及研究组织正积极从事相关IP互联标准方案的制定工作。本文介绍了目前SoC设计中常用的三种片上总线标准,即IBM公司的CoreConnect总线、ARM公司的AMBA总线和OCPIP组织的OCP总线,重点分析和比较了它们的特性,并针对它们不同的特点,阐述其合适的应用领域。

特定应用片上网络的研究综述

特大规模集成电路技术的飞速发展,使得把大量的知识产权(Intellectual Property,IP)核集成到单一的芯片上形成的片上系统成为了今后微电子发展的主流趋势。片上系统面临着许多设计和制造问题,片上网络为解决片上系统的这些问题提供一种行之有效的方案。当前及今后的片上系统都主要面向特定应用或特定应用类,因此,片上网络也是面向特定应用的片上网络,对特定应用片上系统面临的问题、特定片上网络的提出、发展、和主要研究内容进行综述。

基于SoC芯片的嵌入式医学检测设备平台设计

本文将嵌入式系统应用于医学检测设备的开发中,设计了以SoC芯片为核心的嵌入式医学检测设备平台,介绍并探讨了其软硬件系统的基本原理、设计思想、实现方法,并在最后介绍了一个实用的例子。通过医学检测设备软硬件平台,可有效避免设备开发时的重复工作,减少系统的研发时间和成本,缩短推出新产品的时间。

REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES

Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.

浅论嵌入式系统

介绍了嵌入式系统的概念、构成和特点,以及它的发展过程和应用领域。

Stepping Control Method of Linear Displacement Mechanism Driven by TRUM Based on PSoC

A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm.

FlexMEMS-enabled hetero-integration for monolithic FBAR-above-IC oscillators

In this work,a monolithic oscillator chip is heterogeneously integrated by a film bulk acoustic resonator(FBAR)and a complementary metal-oxide-semiconductor(CMOS)chip using FlexMEMS technology.In the 3 D-stacked integrated chip,the thin-film FBAR sits directly over the CMOS chip,between which a 4μm-thick SU-8 layer provides a robust adhesion and acoustic reflection cavity.The proposed system-on-chip(SoC)integration features a simple fabrication process,small size,and excellent performance.The oscillator outputs 2.024 GHz oscillations of-13.79 dB m and exhibits phase noises of-63,-120,and-136 dB c/Hz at 1 kHz,100 kHz,and far-from-carrier offset,respectively.FlexMEMS technology guarantees compact and accurate assembly,process compatibility,and high performance,thereby demonstrating its great potential in SoC hetero-integration applications.