A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder ca...A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder cannot distinguish between train charging current and remote short circuit current.This method uses the principle of energy difference to optimize the optimal mode decomposition number k of VMD;the optimal VMD for DC feeder current is decomposed into the intrinsic modal function(IMF)of different frequency bands.The sample entropy algorithm is used to perform feature extraction of each IMF,and then the eigenvalues of the intrinsic modal function of each frequency band of the current signal can be obtained.The recognition feature vector is input into the support vector machine model based on Bayesian hyperparameter optimization for training.After a large number of experimental data are verified,it is found that the optimal VMD_SampEn algorithm to identify the train charging current and remote short circuit current is more accurate than other algorithms.Thus,the algorithm based on optimized VMD_SampEn has certain engineering application value in the fault current identification of the DC traction feeder.展开更多
A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity re...A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.展开更多
A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differe...A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.展开更多
基金This project supported by The National Natural Science Foundation of China(No.11872253).
文摘A current identification method based on optimized variational mode decomposition(VMD)and sample entropy(SampEn)is proposed in order to solve the problem that the main protection of the urban rail transit DC feeder cannot distinguish between train charging current and remote short circuit current.This method uses the principle of energy difference to optimize the optimal mode decomposition number k of VMD;the optimal VMD for DC feeder current is decomposed into the intrinsic modal function(IMF)of different frequency bands.The sample entropy algorithm is used to perform feature extraction of each IMF,and then the eigenvalues of the intrinsic modal function of each frequency band of the current signal can be obtained.The recognition feature vector is input into the support vector machine model based on Bayesian hyperparameter optimization for training.After a large number of experimental data are verified,it is found that the optimal VMD_SampEn algorithm to identify the train charging current and remote short circuit current is more accurate than other algorithms.Thus,the algorithm based on optimized VMD_SampEn has certain engineering application value in the fault current identification of the DC traction feeder.
文摘A novel, highly linear sampling switch suitable for low-voltage operation is proposed. This switch not only eliminates the nonlinearity introduced by gate-source voltage variation, but also reduces the nonlinearity resuiting from threshold voltage variation, which has not been accomplished in earlier low-voltage sampling switches. This is achieved by adopting a replica transistor with the same threshold voltage as the sampling transistor. The effectiveness of this technique is demonstrated by a prototype design of a sampling switch in 0. 35μm. The proposed sampling switch achieves a spurious free dynamic range of 111dB for a 0. 2MHz, 1.2Vp-p input signal, sampled at a rate of 2MS/s,about 18dB over the Bootstrapped switch. Also, the on-resistance variation is reduced by 90%. This method is especially useful for low-voltage, high resolution ADCs, which is a hot topic today.
基金supported by the National Science and Technology Major Project of China(No.2012ZX03004008)
文摘A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.
