Fast source mask co-optimization method for high-NA EUV lithography

Extreme ultraviolet(EUV)lithography with high numerical aperture(NA)is a future technology to manufacture the integrated circuit in sub-nanometer dimension.Meanwhile,source mask co-optimization(SMO)is an extensively used approach for advanced lithography process beyond 28 nm technology node.This work proposes a novel SMO method to improve the image fidelity of high-NA EUV lithography system.A fast high-NA EUV lithography imaging model is established first,which includes the effects of mask three-dimensional structure and anamorphic magnification.Then,this paper develops an efficient SMO method that combines the gradient-based mask optimization algorithm and the compressivesensing-based source optimization algorithm.A mask rule check(MRC)process is further proposed to simplify the optimized mask pattern.Results illustrate that the proposed SMO method can significantly reduce the lithography patterning error,and maintain high computational efficiency.

Type Synthesis of Self-Alignment Parallel Ankle Rehabilitation Robot with Suitable Passive Degrees of Freedom

The current parallel ankle rehabilitation robot(ARR)suffers from the problem of difficult real-time alignment of the human-robot joint center of rotation,which may lead to secondary injuries to the patient.This study investigates type synthesis of a parallel self-alignment ankle rehabilitation robot(PSAARR)based on the kinematic characteristics of ankle joint rotation center drift from the perspective of introducing"suitable passive degrees of freedom(DOF)"with a suitable number and form.First,the self-alignment principle of parallel ARR was proposed by deriving conditions for transforming a human-robot closed chain(HRCC)formed by an ARR and human body into a kinematic suitable constrained system and introducing conditions of"decoupled"and"less limb".Second,the relationship between the self-alignment principle and actuation wrenches(twists)of PSAARR was analyzed with the velocity Jacobian matrix as a"bridge".Subsequently,the type synthesis conditions of PSAARR were proposed.Third,a PSAARR synthesis method was proposed based on the screw theory and type of PSAARR synthesis conducted.Finally,an HRCC kinematic model was established to verify the self-alignment capability of the PSAARR.In this study,93 types of PSAARR limb structures were synthesized and the self-alignment capability of a human-robot joint axis was verified through kinematic analysis,which provides a theoretical basis for the design of such an ARR.

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory(RRAM).Due to its ultrahigh integration density,RRAM arrays are prone to lithographic variation during the lithography process,introducing electrical variation among different RRAM devices.In this work,an optical physical verification methodology for the RRAM array is developed,and the effects of different layout parameters on important electrical characteristics are systematically investigated.The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments.The read resistance is more sensitive to the locations in the array(~30%)than SET/RESET voltage(<10%).The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%,whereas it reduces RRAM read resistance by 4×,resulting in a higher power and area consumption.As such,we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.

Real-time generation of circular patterns in electron beam lithography

Electron beam lithography(EBL)involves the transfer of a pattern onto the surface of a substrate byfirst scanning a thin layer of organicfilm(called resist)on the surface by a tightly focused and precisely controlled electron beam(exposure)and then selectively removing the exposed or nonexposed regions of the resist in a solvent(developing).It is widely used for fabrication of integrated cir-cuits,mask manufacturing,photoelectric device processing,and otherfields.The key to drawing circular patterns by EBL is the graphics production and control.In an EBL system,an embedded processor calculates and generates the trajectory coordinates for movement of the electron beam,and outputs the corresponding voltage signal through a digital-to-analog converter(DAC)to control a deflector that changes the position of the electron beam.Through this procedure,it is possible to guarantee the accuracy and real-time con-trol of electron beam scanning deflection.Existing EBL systems mostly use the method of polygonal approximation to expose circles.A circle is divided into several polygons,and the smaller the segmentation,the higher is the precision of the splicing circle.However,owing to the need to generate and scan each polygon separately,an increase in the number of segments will lead to a decrease in the overall lithography speed.In this paper,based on Bresenham’s circle algorithm and exploiting the capabilities of afield-programmable gate array and DAC,an improved real-time circle-producing algorithm is designed for EBL.The algorithm can directly generate cir-cular graphics coordinates such as those for a single circle,solid circle,solid ring,or concentric ring,and is able to effectively realizes deflection and scanning of the electron beam for circular graphics lithography.Compared with the polygonal approximation method,the improved algorithm exhibits improved precision and speed.At the same time,the point generation strategy is optimized to solve the blank pixel and pseudo-pixel problems that arise with Bresenham’s circle algorithm.A complete electron beam deflection system is established to carry out lithography experiments,the results of which show that the error between the exposure results and the preset pat-terns is at the nanometer level,indicating that the improved algorithm meets the requirements for real-time control and high precision of EBL.

A 162GHz Self-Aligned InP/InGaAs Heterojunction Bipolar Transistor

An emitter self-aligned InP-based single heterojunction bipolar transistor with a cutoff frequency （fT） of 162GHz is reported. The emitter size is 0.8μm × 12μm, the maximum DC gain is 120, the offset voltage is 0.10V,and the typical breakdown voltage at Ic = 0. 1μA is 3.8V. This device is suitable for high-speed low-power applications,such as OEIC receivers and analog-to-digital converters.

Performance of a Self-Aligned InP/GaInAs SHBT with a Novel T-Shaped Emitter

A self-aligned InP/GalnAs single heterojunction bipolar transistor（HBT） is investigated using a novel T-shaped emitter. A U-shaped emitter layout,selective wet etching,laterally etched undercut, and an air-bridge are applied in this process. The device, which has a 2μm×12μm U-shaped emitter area,demonstrates a common-emitter DC current gain of 170,an offset voltage of 0.2V,a knee voltage of 0.5V, and an open-base breakdown voltage of over 2V. The HBT exhibits good microwave performance with a current gain cutoff frequency of 85GHz and a maximum oscillation frequency of 72GHz, These results indicate that these InP/InGaAs SHBTs are suitable for low-voltage,low-power,and high-frequency applications.

Scalable fabrication of geometry-tunable self-aligned superlattice photonic crystals for spectrum-programmable light trapping

Superlattice photonic crystals (SPhCs) possess considerablepotentials as building blocks for constructing high-performancedevices because of their great flexibilities in opticalmanipulation. From the prospective of practical applications,scalable fabrication of SPhCs with large-area uniformity and precisegeometrical controllability has been considered as one prerequisitebut still remains a challenge.

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

Self-Aligned Titanium Silicide NMOS and 12-Bit Multiplier

Self-aligned Titanium Silicide (Salicide), Light-Doped Drain (LDD) technology was studied. Results show that, this technology suppresses effectivily short-channel effects. The sheet resistance of active region decreases by four times. The sheet resistance of polysilicon gate region decreases by one order of magnitute. Using this technology, the speed of the 3 μm NMOS 12-bits multiplier increases by two times relative to conventional one.

Excellent-Performance AlGaN/GaN Fin-MOSHEMTs with Self-Aligned Al_2O_3Gate Dielectric

A1GaN/GaN fin-shaped metal-oxide-semiconductor high-electron-mobility transistors （fin-MOSHEMTs） with dif- ferent fin widths （30Ohm and lOOnm） on sapphire substrates are fabricated and characterized. High-quality self-Migned Al2O3 gate dielectric underneath an 80-nm T-shaped gate is employed by Muminum self-oxidation, which induces 4 orders of magnitude reduction in the gate leakage current. Compared with conventional planar MOSHEMTs, short channel effects of the fabricated fin-MOSHEMTs are significantly suppressed due to the tri- gate structure, and excellent de characteristics are obtained, such as extremely fiat output curves, smaller drain induced barrier lower, smaller subthreshold swing, more positive threshold voltage, higher transconductance and higher breakdown voltage.

Innovation on Line Cut Methods of Self-aligned Multiple Patterning

Self-aligned multiple patterning (SAMP) can enable the semiconductor scaling before EUV lithography becomes mature for industry use.Theoretically any small size of pitch can be achieved by repeating SADP on same wafer but with challenges of pitch walking and line cut since line cut has to be done by lithography instead of self-aligned method.Line cut can become an issue at sub-30nm pitch due to edge placement error (EPE).In this paper we will discuss some recent novel ideas on line cut after self-aligned multiple patterning.

Simulation research on surface growth process of positive and negative frequency detuning chromium atom lithographic gratings

Chromium atom photolithography gratings are a promising technology for the development of nanoscale length standard substances due to their high accuracy,uniformity,and consistency.However,the inherent difference between the interaction of positive and negative frequency detuning standing wave field and the atoms can cause a difference in the adjacent peak-to-valley heights of the grating in positive and negative frequency detuning chromium atom lithography,which greatly reduces its accuracy.In this study,we performed a controlled variable growth simulation using the semi-classical theoretical model and Monte Carlo method with trajectory tracking and ballistic deposition methods to investigate the influence of key experimental parameters on the surface growth process of positive and negative frequency detuning atomic lithography gratings.We established a theoretical model based on simulation results and summarized empirical equations to guide the selection of experimental parameters.Our simulations achieved uniform positive and negative frequency detuning atomic lithography gratings with a period of 1/4 of the wavelength corresponding to the atomic transition frequency,and adjacent peak-to-valley heights differing by no more than 2 nm,providing an important theoretical reference for the controllable fabrication of these gratings.

面向三重版图曝光约束的详细布线算法

在进一步缩小特征尺寸的问题上,三重版图曝光技术(triplepatterninglithography,TPL)发挥着重要的作用.针对TPL中的版图分解问题,提出了一种基于TPL约束的详细布线算法.将版图分解问题转化为满足同色间距约束和最小间距约束的详细布线问题,使用网格编码的方法来满足2种间距约束;利用与2种间距约束相结合的Hannan网格来提升布线资源的利用率以及布线的速度;结合多源迪杰斯特拉算法进行多端线网的最短路径搜索;最后将布线结果进行版图分解,实现最小化冲突数量和缝合点数量的目标.算法在2.20 GHzCPU和32 GB内存的Ubuntu20.04环境下运行,使用2018年ISPD详细布线比赛的测试集.实验结果表明,与普通详细布线相比,可降低约60%的冲突数量以及70%的缝合点数量.

MOA框架下关键核心技术突破路径研究——以光刻技术领域为例

[研究目的]识别关键核心技术突破路径,加快实现科技自立自强对维护我国产业链供应链安全具有重要的现实意义。[研究方法]基于组织行为视角,通过MOA(动机-机会-能力)分析框架厘清7个变量作为企业突破关键核心技术的前因条件。在此基础上,考虑到我国光刻技术领域的阶段性特征,选取35家光刻技术领域的上市企业为研究对象,并采用NCA和fsQCA方法,分追赶、跟随和攻坚三阶段识别关键核心技术突破路径。[研究结论]机会感知能力是企业加快实现关键核心技术突破的必要条件,且政府支持发挥了普适作用。三阶段共存在7条突破路径,概括为四种驱动类型:追赶阶段的动机-政府-吸收能力驱动型、感知能力驱动型;跟随阶段的政府-吸收能力驱动型;攻坚阶段的政府-适应能力驱动型。突破路径在三阶段间存在演变现象,形成三种演变轨迹包括“缓冲主导轨迹”“转折轨迹”和“主导轨迹”。

从抄配、借校到石印:徐乃昌刊印《说文解字韵谱》考

徐乃昌1925年自来青阁购得元种善堂本《说文解字韵谱》后,拟覆刻出版。徐乃昌请范兆经据《函海》本、李显本抄补缺叶缺字,又先后拟请黄侃、刘葆儒撰写校记,惜校记未能完成。最终,徐乃昌以自藏本《韵谱》为主要底本,又借瞿启甲所藏同版但较为晚印之《韵谱》配补缺叶,于1927年交鸿宝斋石印出版。徐乃昌的书籍出版,在《说文解字韵谱》之后,逐渐从雕版转向石印。梳理徐乃昌刊印《韵谱》的前后始末,也有助于推进对20世纪20年代沪上古籍出版情况的认识。

具有双重显影特性的多用途单分子树脂化学放大光刻胶

化学放大光刻胶(CARs)由于其在分辨率和灵敏度方面的出色性能而广泛应用于光刻领域。本文报道了一种基于单分子树脂的多用途化学放大光刻胶SP8-PAG_(AN),可同时用于365 nm光刻和电子束光刻。该体系主要由螺二芴结构的单分子树脂主体材料(SP-8Boc)和N-(三氟甲基磺酸酯基)蒽-1,9-二羧酰亚胺非离子型光致产酸剂(PAGAn)组成。测试了产酸剂PAGAN在365 nm紫外光激发下的光致产酸效率ΦH+为23%。研究了SP8-PAG_(AN)光刻胶的365 nm光刻和电子束光刻性能。365 nm光刻中,分别利用四甲基氢氧化胺(TMAH,质量分数2.38%)水溶液和正己烷作为显影液,可实现1μm正性和负性光刻图案。电子束光刻中,可实现50 nm Line/Space(L/S)的正性密集线条图案(曝光剂量110μC/cm^(2)),32 nm L/S的负性密集线条图案(曝光剂量40μC/cm^(2))以及19 nm L/3S负性半密集线条图案(曝光剂量96μC/cm^(2))。本研究工作提供了一种具有双重显影特性的多用途单分子树脂化学放大光刻胶的新范例。

A Kernel-Based Convolution Method to Calculate Sparse Aerial Image Intensity for Lithography Simulation

Optical proximity correction (OPC) systems require an accurate and fast way to predict how patterns will be transferred to the wafer.Based on Gabor's 'reduction to principal waves',a partially coherent imaging system can be represented as a superposition of coherent imaging systems,so an accurate and fast sparse aerial image intensity calculation algorithm for lithography simulation is presented based on convolution kernels,which also include simulating the lateral diffusion and some mask processing effects via Gaussian filter.The simplicity of this model leads to substantial computational and analytical benefits.Efficiency of this method is also shown through simulation results.

A New Method to Retrieve Proximity Effect Parameters in Electron-Beam Lithography

A new method for determining proximity parameters α,β ,and η in electron beam lithography is introduced on the assumption that the point exposure spread function is composed of two Gaussians.A single line is used as test pattern to determine proximity effect parameters and the normalization approach is adopted in experimental data transaction in order to eliminate the need of measuring exposure clearing dose of the resist.Furthermore,the parameters acquired by this method are successfully used for proximity effect correction in electron beam lithography on the same experimental conditions.

基于掩模光刻的液晶波前校正器设计与制备

液晶波前校正器通常基于液晶显示器的工艺制备而成,因此其研制成本高、定制难度大。本文基于掩模光刻法制备液晶波前校正器,以实现液晶波前校正器的专用化、低成本研制。基于掩模光刻技术设计并制备了91像素的无源液晶驱动电极,并封装成液晶光学校正单元。设计并制备了驱动连接电路板,实现了液晶光学驱动单元和驱动电路板的匹配对接。对液晶波前校正器响应特性进行检测。结果显示,其相位调制量为5.5个波长,响应时间为224 ms。利用Zygo干涉仪进行球面波的产生和静态倾斜像差的校正。结果显示,其可以产生正负离焦波前,且对水平倾斜像差校正后,Zernike多项式中第一项的值从1.18降至0.16,校正幅度达86%,实现了像差的有效校正。本文的研究工作可为液晶波前校正器的研制提供新思路,进而拓宽其应用领域和场景。

光栅干涉式触觉传感器

因光学式触觉传感器有着灵敏度高、抗干扰能力强等优点,提出了一种基于亚波长金属光栅干涉的触觉传感器。首先,基于等效介质理论和薄膜干涉理论对触觉传感器的传感原理进行介绍;接着,通过纳米压印工艺和真空蒸发镀膜工艺在柔性中间聚合物片材(IPS)表面制作亚波长金属光栅,通过光刻工艺用SU—8光刻胶将亚波长金属光栅以固定间距平行离面放置,使其透射光强随接触力的施加而改变;最后,对光栅触觉传感器进行一系列力加载实验,实验结果表明:该触觉传感器的平均力分辨率可达到0.0003N/Gray以上,平均测量误差为6.3%。通过小型化设计,可以用于机械手上实现触觉传感功能。