A 0.5–3.0 GHz SP4T RF switch with improved body self-biasing technique in 130-nm SOI CMOS

A single-pole four-throw(SP4T)RF switch with charge-pump-based controller is designed and implemented in a commercial 130-nm silicon-on-insulator(SOI)CMOS process.An improved body self-biasing technique based on diodes is utilized to simplify the controlling circuitry and improve the linearity.A multistack field-effect-transistor(FET)structure with body floating technique is employed to provide good power-handling capability.The proposed design demonstrates a measured input 0.1-d B compression point of 38.5 d Bm at 1.9 GHz,an insertion loss of 0.27 d B/0.33 d B and an isolation of 35 d B/27 d B at 900 MHz/1.9 GHz,respectively.The overall chip area is only 0.49 mm^2.This RF switch can be used in GSM/WCDMA/LTE frontend modules.

A 3GHz Low-Power and Low-Phase-Noise LC VCO with a Self-Biasing Current Source

A fully integrated 3GHz low-power and low-phase-noise voltage-controlled oscillator （VCO） with a self-biasing current source was implemented in a standard 0.18μm CMOS process. A trade-off between noise and power was realized through the optimization of the improved current source. The VCO can be tuned from 2.83 to 3.25GHz with a 13.8% tuning range. The measured phase noise at 1MHz offset is -111dBc/Hz at a frequency of 3.22GHz while the core circuit draws less than 2mA from a 1.8V supply voltage. These results make the circuit suitable for a 5GHz wireless local area network （WLAN） receiver and 3.4 to 3.6GHz world interoperability for microwave access （WiMAX） application.

Heterojunction between anodic TiO_2/g-C_3N_4 and cathodic WO_3/W nano-catalysts for coupled pollutant removal in a self-biased system

An anodic TiO2/g-C3N4 hetero-junction and cathodic WO3/W were used to build a self-sustained catalytic fuel cell system for oxidizing rhodamine B or triclosan and reducing NO3^--N to N2 simultaneously.The WO3 nano-catalyst was formed in situ by heating and oxidizing a tungsten wire in air.Cyclic voltammetry and current-time curves were used to characterize the electrochemical properties of the electrodes and system.Aeration and activation of molecular oxygen by self-biased TiO2/g-C3N4 led to the formation of reactive oxidizing species in the fuel cell.The mechanism of simultaneous anodic oxidation of pollutants and cathodic reduction of nitrate was proposed.The spontaneously formed circuit and tiny current were used simultaneously in treating two kinds of wastewater in the reactor chambers,even without light illumination or an external applied voltage.This new catalytic pollution control route can lower energy consumption and degrade many other kinds of pollutants.

Preparation and Magnetic Properties of SrFe12O19 Ferrites Suitable for Use in Self-Biased LTCC Circulators

Strontium ferrites with different Bi2O3 content are prepared by the solid phase method, and their magnetic properties are investigated primarily. The Bi2O3 additive and sintering temperature separately exhibit a strong effect on the sintering density, crystal structure, and magnetic properties of the ferrites. As to the ferrites with 3 wt% Bi2O3, the relatively high sintering density ρs, saturation magnetization Ms, and intrinsic coercivity HCi can be obtained at a low sintering temperature of 900℃ even much lower. Furthermore, the effective magnetic anisotropy constant Keff and magnetic anisotropy field Ha of the ferrites are calculated from the magnetization curve by the law of approach to saturation. It is suggested that the low-temperature sintered SrFe12O19 ferrites with Ms of 285.6 kA/m and Ha of 1564.6 kA/m possess a significant potentiality for applying in the self-biased low-temperature co-fired ceramics circulators from 34 to 40GHz.

The Effect of a Multihollow Cathode on the Self-Bias Voltage of Methane RF Discharge Used for a-C:H Deposition

In this work we report the measurement of the self-bias voltage of radiofrequency (RF) capacitevely coupled plasma, with a multihollow cathode and methane precursor, used for amorphous hydrogenated carbon (a- C:H) thin film deposition. The plasma is produced in the incident power and pressure ranges between 20 - 300 W and 10 - 100 mTorr, respectively. It was found that the self-bias voltage Vdc is a linear function of the square root of the incident power WRF. The relationship between the self-bias voltage and gas pressure P is established;this gives an empirical relation for (p/p0)y . From this result, the pressure p0 corresponding to the transition from hollow cathode effect to hollow cathode arc effect is determined.

Fully-integrated ultra-wide band LNA in 0.18μm CMOS technology for 3-10 GHz applications

The paper presents a fully integrated ultra-wide band(UWB)low noise amplifier(LNA)for 3-10 GHz applications.It employs self-biased resistive-feedback and current-reused technique to achieve wide input matching and low power characteristics.An improved biased architecture is adopted in the second stage to attain a better gain-compensation performance.The design is verified with TSMC standard 1 P6 M 0.18μm RF CMOS process.The measurement results show that the parasitic problem of the transistors at high frequencies is solved.A high and flat S21 of 9.7±1.5 dB and the lowest NF 3.5 dB are achieved in the desired frequency band.The power consumption is only 7.5 mA under 1.6 V supply.The proposed LNA achieves broadband flat gain,low noise,and high linearity performance simultaneously,allowing it to be used in 3-10 GHz UWB applications.

Design of radiation hard phase-locked loop at 2.5 GHz using SOS-CMOS

A radiation hard phase-locked loop （PLL） is designed at 2.5 GHz using silicon on sapphire complementary metal-oxide-semiconductor process. Radiation hardness is achieved through improving circuit design without sacrificing real estate. Stability is guaranteed by a fully self-bias architecture. The lock time of PLL is minimized by maximizing the loop bandwidth. Frequency tuning range of voltage controlled oscillator is significantly enhanced by a novel load configuration. In addition, multiple bias stages, asynchronous frequency divider, and silicon on sapphire process jointly make the proposed PLL more radiation hard. Layout of this PLL is simulated by Cadence Spectre RF under both single event effect and total induced dose effect. Simulation results demonstrate excellent stability, lock time 〈 600 ns, frequency tuning range [1.57 GHz, 3.46 GHz], and jitter 〈 12 ps. Through comparison with PLLs in literatures, the PLL is especially superior in terms of lock time and frequency tuning range performances.

Inductorless CMOS Low Noise Amplifier for Multiband Application in 0.1–1.2 GHz

A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.

Self-biased magnetoelectric effect in(Pb, Zr)TiO_3/metglas laminates by annealing method

Fe BSi C metglas was annealed at an optimized condition（350 °C, 5 min） to achieve the mixed phases with pristine amorphous phase and crystallization phase.With such annealed metglas, a self-biased magnetoelectric（ME） laminate of metglas/Pb（Zr, Ti）O3/metglas was fabricated. Without any external magnetic field, the composite exhibits the ME coefficient aE31 of 103 m V/（cm Oe） at1 k Hz and 15.5 V/（cm Oe） at electromechanical resonance frequency. The induced ME voltage shows a good linear relation to the applied AC magnetic field with amplitude as low as 10-7T at 1 k Hz. It is expected that such self-biased ME composites provide a practical application of economical and compact magnetic sensors.

A self-biased PLL with low power and compact area

A new low power, low phase jitter, compact realization, and sell-biased PLL, which is fabricated on SMIC 40 nm CMOS technology is introduced. The proposed self-biased PLL eliminates extra band gap biasing circuits, and internally generates all the biasing voltages and currents. Meanwhile, all of the PLL dynamic loop parameters, such as loop bandwidth, natural frequency, damping factors are kept constant adaptively. By optimizing the circuit structures, the perfect unity of chip estate, power dissipation, phase jitter, and loop stability is achieved. THe PLL consumes 4.2 mW of power tinder 1.1 V/2.5 V voltage supply at 2.4 GHz VCO frequency, while occupying a die area of less than 0.02 mmz （180 × 110 μm2）, and the typical period jitter （RMS） is around 2.8 ps.

Broadband low noise amplifier design based on self-bias

A 20 GHz-24 GHz three-stage low noise amplifier(LNA) was implemented using the GaAs pseudomorphic high electron mobility transistor(PHEMT) process. The schematic design and optimization of the LNA were carried out using advanced design system(ADS). The three-stage series structure is used to increase the gain of the amplifier. Additionally, a self-biasing network and negative feedback circuit can expand the bandwidth while increasing the stability of the circuit and obtaining better input matching and noise. The test results show that the gain in the 20 GHz-24 GHz band is greater than 20 dB, the noise figure(NF) is 2.1 dB, and the input and output reflection coefficients are less than-10 dB, which meets the design requirements. The amplifier serves a wide range of applications, including wireless communications, radar systems, satellite communications, and other areas that require high-frequency amplification to enhance system performance and sensitivity.

An offset-insensitive switched-capacitor bandgap reference with continuous output

An improved switched-capacitor bandgap reference with a continuous output voltage of 1.26 V has been implemented with Chartered 0.35-μm 5-V CMOS process. The output offset voltage, induced by non-ideal characteristics of operational amplifier and bias current generator, is suppressed by the proposed sample-and-hold circuit and self-bias technique. Experimental results show that the proposed circuit operates properly under a supply voltage varying from 3 to 5 V. The measured temperature coefficient is 112 ppm/℃ and the power supply rejection ratio of output voltage without any filtering capacitor is -40 dB and -33 dB at 100 Hz and 10 MHz, respectively.