Reliability evaluation on sense-switch p-channel flash

In this paper,the reliability of sense-switch p-channel flash is evaluated extensively.The endurance result indicates that the p-channel flash could be programmed and erased for more than 10000 cycles;the room temperature read stress shows negligible influence on the p-channel flash cell;high temperature data retention at 150℃ is extrapolated to be about 5 years and 53 years corresponding to 30% and 40% degradation in the drive current,respectively.Moreover,the electrical parameters of the p-channel flash at different operation temperature are found to be less affected.All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.

Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.

Flash型FPGA的编程及干扰抑制技术

为了降低Flash型现场可编程门阵列(FPGA)中的Flash开关单元在编程中受到编程干扰对阈值电压的影响,提高驱动能力的一致性,提出了高位宽编程技术与常用的选择管隔离技术相结合来抑制编程干扰的方法。通过高位宽编程技术降低编程过程中栅扰对同一行中Flash开关单元阈值电压的影响;通过选择管隔离技术降低编程过程中漏扰对同一列中Flash开关单元阈值电压的影响;采用NMOS晶体管作为隔离管实现自限制编程,对Flash开关单元的阈值电压进行精确控制。实验结果表明,参照系统等效门数为百万门级Flash型FPGA中的Flash开关阵列形式2 912 bit×480 WL×20 Bank,按最差条件进行479次漏扰测试,Flash开关单元受编程干扰后的阈值电压漂移约为0 V;进行时长为40μs的栅扰测试,Flash开关单元受编程干扰后阈值电压漂移约为0.02 V。