图像感知系统与图像显示系统与人类视觉功能接近,容易被人们所接受。在车载ADAS/ADS中,图像感知系统与图像显示系统得到广泛的应用。高清数字摄像头和高清显示设备的应用,催生了新的高速链路传输技术,SerDes作为其中的佼佼者,被广泛采...图像感知系统与图像显示系统与人类视觉功能接近,容易被人们所接受。在车载ADAS/ADS中,图像感知系统与图像显示系统得到广泛的应用。高清数字摄像头和高清显示设备的应用,催生了新的高速链路传输技术,SerDes作为其中的佼佼者,被广泛采用。芯片厂商提供了各种评价SerDes高速链路的传输性能的方案,其中Link Margin测试具有速度快,可操作性强,测试结果准确,容易实现现场测试等特点。介绍了一种简单易操作,可平台测试,也可实车测试的SerDes Link Margin测试方案。展开更多
This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A...This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.展开更多
A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.展开更多
文摘图像感知系统与图像显示系统与人类视觉功能接近,容易被人们所接受。在车载ADAS/ADS中,图像感知系统与图像显示系统得到广泛的应用。高清数字摄像头和高清显示设备的应用,催生了新的高速链路传输技术,SerDes作为其中的佼佼者,被广泛采用。芯片厂商提供了各种评价SerDes高速链路的传输性能的方案,其中Link Margin测试具有速度快,可操作性强,测试结果准确,容易实现现场测试等特点。介绍了一种简单易操作,可平台测试,也可实车测试的SerDes Link Margin测试方案。
基金supported by the National Natural Science Foundation of China under Grant No. 61006027the New Century Excellent Talents Program under Grant No. NCET-10-0297
文摘This paper presents the implementation of a multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used in the transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is also described. With an on-chip fully integrated phase locked loop, the transceiver works at data rates of 100 Mb/s, 400 Mb/s, and 800 Mb/s, supporting three different operating modes of S100b, S400b, and S800b for IEEE 1394b. The chip has been fabricated using 0.13 μm technology. The die area of transceiver is 2.9×1.6 mm2^ including bonding pads and the total power dissipation is 284 mW with 1.2 V core supply and 3.3 V input/output supply voltages.
文摘A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given. A new method to optimize loop parameters based on low-jitter in PLL is also introduced. A low-jitter 1.25GHz Serdes is implemented in a 0.35μm standard 2P3M CMOS process. The result shows that the RJ （random jitter） RMS of 1.25GHz data rate series output is 2. 3ps （0. 0015UI） and RJ （1 sigma） is 0. 0035UI. A phase noise measurement shows - 120dBc/Hz@100kHz at 1111100000 clock-pattern data out.
