Stability of Nonlinear Feedback Shift Registers with Periodic Input

The stability of Non-Linear Feedback Shift Registers(NFSRs)plays an important role in the cryptographic security.Due to the complexity of nonlinear systems and the lack of efficient algebraic tools,the theorems related to the stability of NFSRs are still not well-developed.In this paper,we view the NFSR with periodic inputs as a Boolean control network.Based on the mathematical tool of semi-tensor product(STP),the Boolean network can be mapped into an algebraic form.Through these basic theories,we analyze the state space of non-autonomous NFSRs,and discuss the stability of an NFSR with periodic inputs of limited length or unlimited length.The simulation results are provided to prove the efficiency of the model.Based on these works,we can provide a method to analyze the stability of the NFSR with periodic input,including limited length and unlimited length.By this,we can efficiently reduce the computational complexity,and its efficiency is demonstrated by applying the theorem in simulations dealing with the stability of a non-autonomous NFSR.

On observability of Galois nonlinear feedback shift registers over finite fields

Observability ensures that any two distinct initial states can be uniquely determined by their outputs,so the stream ciphers can avoid unobservable nonlinear feedback shift registers(NFSRs)to prevent the occurrence of equivalent keys.This paper discusses the observability of Galois NFSRs over finite fields.Galois NFSRs are treated as logical networks using the semi-tensor product.The vector form of the state transition matrix is introduced,by which a necessary and sufficient condition is proposed,as well as an algorithm for determining the observability of general Galois NFSRs.Moreover,a new observability matrix is defined,which can derive a matrix method with lower computation complexity.Furthermore,the observability of two special types of Galois NFSRs,a full-length Galois NFSR and a nonsingular Galois NFSR,is investigated.Two methods are proposed to determine the observability of these two special types of NFSRs,and some numerical examples are provided to support these results.

Analysis of the Design Methods of Word Oriented Linear Feedback Shift Registers

Based on analysis of the structure characteristics and implementation methods of some representative word oriented linear feedback shift registers （LFSRs） in several modem software oriented stream ciphers, this paper firstly classifies the word oriented LFSRs into two classes： the machine instruction type and the arithmetic type. The similarities and differences between each type are illustrated by concrete examples. Then we give a detailed analysis about the word oriented LFSRs in each category from design structure, cryptographic properties and implementation issue aspects. Finally, some basic design criteria for modem word oriented LFSRs and suitable for software implementation are summarized.

Design of Feedback Shift Register of Against Power Analysis Attack

Stream ciphers based on linear feedback shift register(LFSR)are suitable for constrained environments,such as satellite communications,radio frequency identification devices tag,sensor networks and Internet of Things,due to its simple hardware structures,high speed encryption and lower power consumption.LFSR,as a cryptographic primitive,has been used to generate a maximum period sequence.Because the switching of the status bits is regular,the power consumption of the LFSR is correlated in a linear way.As a result,the power consumption characteristics of stream cipher based on LFSR are vulnerable to leaking initialization vectors under the power attacks.In this paper,a new design of LFSR against power attacks is proposed.The power consumption characteristics of LFSR can be masked by using an additional LFSR and confused by adding a new filter Boolean function and a flip-flop.The design method has been implemented easily by circuits in this new design in comparison with the others.

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

Ethernet Controller SoC Design and Its Low-Power DFT Considerations

In this paper, an Ethernet controller SoC solution and its low power design for testability （DFT） for information appliances are presented. On a single chip, an enhanced one-cycle 8-bit micro controller unit （MCU）, media access control （MAC） circuit and embedded memories such as static random access memory （SRAM）, read only memory （ROM） and flash are all integrated together. In order to achieve high fault coverage, at the same time with low test power, different DFT techniques are adopted for different circuits： the scan circuit that reduces switching activity is implemented for digital logic circuits; BIST-based method is employed for the on-chip SRAM and ROM. According to the fault-modeling of embedded flash, we resort to a March-like method for flash built in self test （BIST）. By all means above, the result shows that the fault coverage may reach 97%, and the SoC chip is implemented successfully by using 0.25 μm two-poly four-metal mixed signal complementary metal oxide semiconductor （CMOS） technology, the die area is 4.8×4.6 mm^2. Test results show that the maximum throughput of Ethemet packets may reach 7Mb·s^1.

Blind reconstruction of linear scrambler

An algorithm based on eigenanalysis technique and Walsh-Hadamard transform （WriT） is proposed. The algorithm contains two steps. Firstly, the received sequence is divided into temporal windows, and a covariance matrix is computed. The linear feedback shift register （LFSR） sequence is reconstructed from the first eigenvector of this matrix. Secondly, equations according to the recovered LFSR sequence are constructed, and the Walsh spectrum corresponding to the equations is computed. The feedback polynomial of LFSR is estimated from the Walsh spectrum. The validity of the algorithm is verified by the simulation result. Finally, case studies are presented to illustrate the performance of the blind reconstruction method.

Evolutionary Random Sequence Generators Based on LFSR

Random numbers play a crucial role in modern security schemes. Couple to the rapid development of cryptography, the strength of security protocols and encryption algorithms consumingly relies on the quality of random number. With simple architecture and faster speed, linear feedback shift register often is selected in many applications. However, the random sequence generated by LFSR can not meet the demand of unpredictability for secure mechanism. Genetic algorithm improves the linear property of LFSR and constructs a novel random sequence generator with longer period and complex architecture.

ON THE LINEAR COMPLEXITY OF FCSR SEQUENCES

The linear complexity of a new kind of keystream sequences.FCSR sequences,is discussed by use of the properties of cyclotomic polynomials.Based on the results of C.Seo's,an upper bound and a lower bound on the linear complexity of a significant kind of FCSR sequences—l-sequences are presented.

A Note on Determine the Greatest Common Subfamily of Two NFSRs by Grbner Basis

For nonlinear feedback shift registers （NFSRs）, their greatest common subfamily may be not unique. Given two NFSRs, the authors only consider the case that their greatest common subfamily exists and is unique. If the greatest common subfamily is exactly the set of all sequences which can be generated by both of them, the authors can determine it by Grobner basis theory. Otherwise, the authors can determine it under some conditions and partly solve the problem.

Low Cost BIST Scheme Using LFSR-RC Reseeding

A novel BIST scheme for reducing the test storage( TS) is presented. The proposed approach relies on a two-dimensional compression scheme,which combines the advantages of the previous LFSR reseeding scheme and test set embedding technique based on ring counters( RCs) to improve the encoding efficiency. It presents a general method to determine the probability of encoding as a function of the number of specified bits in the test cube,the length of the LFSR and the width of the test set,and conclude that the probability of encoding a n-bit test cube with s specified bits using a( smax+ 1 + 20 / n)-stage LFSR with a fixed polynomial is1- 10-6. Experimental results for the ISCAS '89 benchmark circuits show that compared with the previous schemes,the proposed scheme based on LFSR-RC reseeding requires 57% less TS and 99. 1% test application time( TAT) with simple and uniform BIST control logic.

Generalization of Multiplication M-Sequences over Fp and Its Recip­rocal Sequences

M_(p)-Sequences or M-Sequence over Fp not used so much in current time as binary M-Sequences and it is pending with the difficult to construct there coders and decoders of M_(p)-Sequences further these reasons there is expensive values to construct them but the progress in the technical methods will be lead to fast using these sequences in different life’s ways,and these sequences give more collection of information and distribution them on the input and output links of the communication channels,building new systems with more complexity,larger period,and security.In current article we will study the construction of the multiplication M_(p)-Sequence{z_(n)}and its linear equivalent,this sequences are as multiple two sequences,the first sequence{Sn}is an arbitrary M_(p)-Sequence and the second sequence{ζ_(n)}reciprocal sequence of the first sequence{S_(n)},length of the sequence{z_(n)},period,orthogonal and the relations between the coefficients and roots of the characteristic polynomial of f(x)and it’s reciprocal polynomial g(x)and compare these properties with corresponding properties in M-Sequences.

Study the Multiplication M-sequences and Its Reciprocal Sequences

M-Sequences play a big important role,as the other binary orthogonal sequences,for collection the information on the input links and distribution these information on the output links of the communication channels and for building new systems with more complexity,larger period,and security,through multiplication these sequences.In our article we try to study the construction of the multiplication sequence{zn}and its linear equivalent,this multiplication sequence is as multiple two sequences,the first sequence{an}is an arbitrary M-sequence and the second sequence{bn}is not completely different but is the reciprocal sequence of the first sequence{an}that is the reciprocal sequence has characteristic polynomial g(x)is reciprocal of f(x),which is the characteristic polynomial of the first sequence{an},also we will study the linear equivalent of the multiplication sequence{zn}and we will see that the length of the linear equivalent of{zn}is equal to((deg f(x))^(2)-deg(f(x)).

Finding Non-liner Register on Binary M-Sequence Generating Binary Multiplication Sequence

In the current time there is an important problem that is for a received linear or nonlinear binary sequence{z_(n)}how we can find the nonlinear feedback shift register and its linear equivalent which generate this sequence.The linear orthogonal sequences,special M-Sequences,play a big role in these methods for solving this problem.In the current research trying give illuminations about the methods which are very useful for solving this problem under short sequences,and study these methods for finding the nonlinear feedback shift register of a multiplication sequence and its linear equivalent feedback shift register of a received multiplication binary sequence{z_(n)}where the multiplication on h degrees of a binary linear sequence{a_(n)},or finding the equivalent linear feedback shift register of{z_(n)},where the sequence{z_(n)}of the form M-sequence,and these methods are very effectively.We can extend these methods for the large sequences using programming and modern computers with large memory.

Analysis, Design, and Test of CDMA LFSR with Offset Mask Using Standard ICs

Hardware implementation of Linear Feedback Shift Register (LFSR) plays a great and very important role in communication systems, and in many security devices. In this paper, a design of LFSR with offset mask has been presented, for Direct Sequence Code Division Multiple Access (DS-CDMA) applications. Integrated electronic components have been used. An accessible model facilitating the synthesis on Printed Circuit Boards (PCB) and implementation on Field Programmable Gate Array (FPGA) is offered. In addition, a temporal and spectral analysis of the circuit is performed in order to validate the design. This latter facilitates the generation of pseudo-random codes based on LFSR and their integration into electronic systems.

Security analysis of a new stream cipher

In this paper, we analyze the security of a new stream cipher-COSvd（2,128）. This cipher was proposed by E. Filiol et al. at the ECRYPT SASC＇2004 （The State of the Art of Stream Ciphers）. It uses clock-controlled non-linear feedback registers together with an S-box controlled by a chaotic sequence and was claimed to prevent any existing attacks. However, our analysis shows that there are some serious security flaws in the design of the S-box, resulting in heavy biased byte distribution in the keystream. In some broadcast applications, this flaw will cause a ciphertext-only attack with high success rate. Besides, there are also many security flaws in other parts of the cipher. We point out these flaws one by one and develop a divide-and-conquer attack to recover the secret keys from O（2^26）-byte known plaintext with success rate 93.4597% and complexity O（2^113）, which is much lower than 2^512, the complexity of exhaustive search.

REAL—TIME AND GENERAL—PURPOSE TIME—COMPRESSED CORRELATOR

The time-compressed correlator has been widely applied in active sonar design since 1960's. The principles of DELTIC and MACORMATIC cannot be directly used in passive sonar due to the limitation of sampling frequency and data length. Otherwise the input data will be missed periodically in the system output. An Alternative Access Time-Compressed Correletor (ALATIC) is proposed in this paper. By using a buffer register the correlation operation of arbitrary length can be done in real time. This model is a general purpose correlator, which can be used in both active and passive sonars. The running positive order and inverse order register and the shift positive order and inverse order model are presented. The hardware implementation and the flow chart graph of ALATIC are also described. The model presented in this paper can be used in digital sonar design.

A Loop-Based Apparatus for At-Speed Self-Testing

At-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transit ion- graph of t he proposed B IS T scheme are analyzed. B ased on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.

Scan-Based Attack on Stream Ciphers: A Case Study on eSTREAM Finalists

Scan-based design for test （DFT） is a powerful and the most popular testing technique. However, while scan-based DFT improves test efficiency, it also leaves a side channel to the privacy information stored in the chip. This paper investigates the side channel and proposes a simple but powerful scan-based attack that can reveal the key and/or state stored in the chips that implement the state-of-the-art stream ciphers with less than 85 scan-out vectors.