A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

Development of Physical Library for Short Channel CMOS / SOI Integrated Circuits

An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.

Shot Noise Suppression in a Quantum Point Contact with Short Channel Length

An experimental study on the current shot noise of a quantum point contact with short channel length is reported. The experimentally measured maximum energy level spacing between the ground and the first excited state of the device reached up to 7.5meV, probably due to the hard wall confinement by using shallow electron gas and sharp point contact geometry. The two-dimensionM non-equilibrium shot noise contour map shows noise suppression characteristics in a wide range of bias voltage. Fano factor analysis indicates spin-polarized transport through a short quantum point contact.

Static characteristics and short channel effect in enhancement-mode AlN/GaN/AlN N-polar MISFET with self-aligned source/drain regions

This paper aims to simulate the I–V static characteristic of the enhancement-mode（E-mode） Npolar GaN metal–insulator–semiconductor field effect transistor（MISFET） with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.

Simulation study on short channel double-gate junctionless field-effect transistors

We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.

New aspects of HCI test for ultra-short channel n-MOSFET devices

Hot carriers injection （HCI） tests for ultra-short channel n-MOSFET devices were studied. The experimental data of short channel devices （75-90 nm）, which does not fit formal degradation power law well, will bring severe error in lifetime prediction. This phenomenon usually happens under high drain voltage （Vd） stress condition. A new model was presented to fit the degradation curve better. It was observed that the peak of the substrate current under low drain voltage stress cannot be found in ultra-short channel device. Devices with different channel lengths were studied under different Vd stresses in order to understand the relations between peak of substrate current （/sub） and channel length/stress voltage.

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator （PDSOI） nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences （IMECAS）. Mechanisms determining short-channel effects （SCE） in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect （RSCE） than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

Short channel carbon nanotube thin film transistors with high on/off ratio fabricated by two-step fringing field dielectrophoresis

薄电影晶体管(CNT-TFTs ) 制造被表明的为碳 nanotube 的一个二拍子的圆舞 fringing 地 dielectrophoretic 集会方法。浓密地排列的 CNT 数组顺序在来源和排水管电极被装配它形成排列 CNT 数组的串联结构。串联结构还原剂滤的可能性在隧道的金属性的小径，它对设备性能有益。这样，两高开／关水流比率我 在 /I 离开 ( 多达 10 7) 和高产量水流密度(8.5 A/m ) 在短隧道长度被获得(1-2.5 ? m ) CNT-TFTs。装配策略的报导 CNT 是选择、高度有效的地点，它能被放大直到大尺寸底层并且导致 CNT-TFTs 制造的高产量。

Suppression to the cross-channel interference based on the short time Fourier transform

A new cross-channel interference suppression method is proposed to decrease the cross-channel interference in beat signals based on the short time Fourier transform(STFT)and the inverse short time Fourier transform(ISTFT)when the dual-orthogonal polarimetric frequency-modulated continuous wave(FMCW)radar adopts the opposite-slope linear frequency modulation signal pair in the simultaneous measurement mode.The STFT is applied only on the signals in the cross-interference intervals in the four polarimetric channels to decrease the computation complexity.A mask matrix for suppressing the interference is constructed using the constant false alarm ratio(CFAR)detection on the spectrograms by the STFT.The simulative results show that the cross-channel interference is efficiently suppressed by the proposed method.The comparison between the proposed method and the rejection method verifies the improved performance of the proposed method.

Short Baseline Positioning with an Improved Time Reversal Technique in a Multi-path Channel

在水下面的一条多路径隧道的存在极大地减少放系统的短基线的精确性。在这份报纸，到放系统的短基线的一面时间颠倒镜子的申请被调查。时间颠倒镜子技术允许声学的信号更好集中在未知环境，它有效地减少了多路径的扩大声学的信号象一样改进了集中的信号。时间颠倒操作员的 signal-to-noise 比率(SNR ) 极大地增加了并且能被 ensonifying 获得水。这种技术被环境并且因此少些影响对复杂的浅水环境更适用。数字模拟和水池实验被用来表明这种技术的效率。

单侧双通道内镜治疗重度腰椎管狭窄症的近期疗效分析

目的探讨单侧双通道内镜治疗重度腰椎管狭窄症的近期疗效及对患者硬膜囊面积、功能恢复情况的影响。方法前瞻性选取2021年1月至2023年1月衢州市人民医院收治的重度腰椎管狭窄症患者60例为研究对象,采用随机数字表法分为观察组和对照组,各30例。观察组实施单侧双通道内镜技术,对照组实施传统腰椎后路椎板开窗减压术,比较两组患者手术效果、硬膜囊面积变化、功能恢复及并发症发生情况。结果观察组患者总优良率为93.33%,高于对照组的73.33%,差异有统计学意义(P<0.05)。与术前比较,术后1个月两组患者硬膜囊面积均增大,且观察组大于对照组,差异均有统计学意义(均P<0.05)。与术前比较,术后3个月两组患者日本骨科协会腰痛评分均升高,Oswestry功能障碍指数均降低,且观察组均上述指标均优于对照组,差异均有统计学意义(均P<0.05)。观察组和对照组并发症发生率分别为10.00%和20.00%,两组比较差异无统计学意义(P>0.05)。结论单侧双通道内镜治疗重度腰椎管狭窄症近期疗效显著,可明显减轻患者术后疼痛程度,改善患者腰椎功能。

基于购买漏斗模型的多渠道网络广告效应研究

从企业发起渠道(firm-initiated contacts,FICs)和客户发起渠道(customer-initiated contacts,CICs)两方面,探讨了不同网络广告的短期及长期效应。通过对网络广告短期效应和长期效应的综合测评,以期为企业营销合理分配广告预算提供实践指导。实证研究发现,从短期来看,FICs品牌型广告的即时效应最大,从长期来看,FICs广告有着最强的长期累积效应,特别是短信广告。FICs广告的效应持续时间比CICs广告的效应持续时间更长。CICs品牌型搜索广告在首页访问阶段产生了更高的效应,CICs通用型搜索广告在主页访问和详情页访问阶段的效应较为相近,而FICs广告能更有效地吸引客户转到特定的产品详情页面。

15 nm Bulk nFinFET器件性能研究及参数优化

为研究Bulk FinFET工作时基本结构参数、器件温度和栅极材料对其性能的影响,建立了一个15 nm n型Bulk FinFET器件模型,仿真分析了不同栅长、鳍宽、鳍高、沟道掺杂浓度、器件工作温度、栅极材料对器件性能的影响,发现增长栅长、降低鳍宽和增加鳍高有助于抑制短沟道效应;1×10^(17)cm^(-3)以下的低沟道掺杂浓度对器件特性影响不大,但高掺杂会使器件失效;器件工作温度的升高会导致器件性能的下降;采用高K介质材料作为栅极器件性能优于传统材料SiO_(2)。

一种面向112 Gb/s PAM4接收机的自适应均衡设计方案

提出了一种适用于超短距离(Very Short Reach,VSR)信道、面向112 Gb/s PAM4(Pulse Amplitude Modulation 4)接收机的自适应均衡设计方案。在该方案中,接收机前端利用3个连续时间线性均衡器(Continuous Time Linear Equalizer,CTLE)对信号分别在高频、中频和低频进行补偿,可变增益放大器(Variable Gain Amplifier,VGA)和饱和放大器(Saturation Amplifier,SatAmp)则用于对信号幅值的缩放。除了3个数据采样器外,引入4个辅助采样器用于进一步改善阈值自适应算法性能。同时,采用符号最小均方算法,利用接收端数据采样器和辅助采样器之间的偏移推动辅助参考电压收敛到信号星座电平,从而确保PAM4接收信号的眼图在垂直方向上3个眼睛具有相等的间隔和恒定的信噪比(Signal-to-Noise Ratio,SNR)。仿真结果表明,所提出的112 Gb/s PAM4接收机能够在损耗为15 dB的信道上实现小于10~(-12)的误码率,并且具有良好的眼图性能,其最差眼高为75 mV,眼宽为0.34 UI(Unit Interval),与传统方案相比具有显著的性能提升。

注意力去噪与复数LSTM的时变信道预测算法

随着无线通信技术的发展,高速场景下通信技术的研究也越来越广泛,其中获取到准确的信道状态信息对提升无线通信系统的性能具有重要的意义。针对正交频分复用系统在高速场景下,现有信道预测算法未考虑噪声影响及预测精度低的问题,提出了一种注意力去噪与复数卷积LSTM的时变信道预测算法。首先,设计了一种通道注意力信道去噪网络对信道状态信息进行去噪处理,降低了噪声对信道状态信息的影响。然后,提出了基于复数卷积层和长短期记忆网络的信道预测模型,对去噪后历史时刻的信道状态信息进行特征提取,并且对未来时刻的信道状态信息进行预测;改进后的LSTM预测模型增强了对信道时序特征的提取能力,提高了信道预测的精度。最后,结合Adam优化器对未来时刻信道状态信息进行预测输出。仿真结果表明:与对比算法相比,所提基于注意力去噪与复数卷积LSTM的时变信道预测算法对信道状态信息的预测精度更高,能够适用于高速移动场景下的时变信道预测。

基于BSIM⁃CMG紧凑模型的NSFET直流特性建模

随着半导体制造工艺技术的发展,纳米片场效应晶体管(NSFET)成为下一代集成电路的核心器件,建立能准确描述NSFET特性的SPICE模型对提高基于NSFET的集成电路设计的成功率和缩短先进工艺的开发周期至关重要。结合Sentaurus TCAD仿真与伯克利短沟道绝缘栅场效应晶体管公共多栅(BSIM⁃CMG)紧凑模型,对NSFET进行直流特性建模。使用器件模型提取工具XModel提取器件的直流特性参数,包括单器件参数提取、温度及自热效应参数提取。结果表明,单器件直流特性参数提取平均误差小于5%,温度及自热效应的参数提取结果精准度较好,验证了模型的准确性。最后,构建并验证分组模型与工艺角模型。这些模型能准确描述不同尺寸和工艺波动对NSFET器件特性的影响,为加快高性能、低功耗NSFET的开发提供理论参考和实践指导。

大型水利工程梯级泵站短期优化调度方案

针对泵站高能耗难题,采用粒子群优化算法对南水北调东线徐洪河段的短期经济性调度方案进行研究.基于水量平衡方法,耦合流量、水位、蓄量及水力损失函数关系式,动态模拟渠道水情变化过程.将泵站扬程动态调整过程中产生的电费纳入考虑范围,以调度期内梯级输水系统产生的总电费和调控后水位与目标偏差最小为优化目标,其中目标水位为适应短期内调节的梯级扬程优化分配结果.基于实际运行数据对模型结果进行分析和验证,结果表明:渠道水情模拟方法的模拟精度较高,水位模拟值与实测值平均误差在10 cm左右;梯级短期优化调度模型引入目标水位增强了优化效果,进一步减少4.7元/万m3用电费用,优化方案的单位运行成本相比实际调度可有效降低6.7%.