Static characteristics and short channel effect in enhancement-mode AlN/GaN/AlN N-polar MISFET with self-aligned source/drain regions

This paper aims to simulate the I–V static characteristic of the enhancement-mode（E-mode） Npolar GaN metal–insulator–semiconductor field effect transistor（MISFET） with self-aligned source/drain regions.Firstly, with SILVACO TCAD device simulation, the drain–source current as a function of the gate–source voltage is calculated and the dependence of the drain–source current on the drain–source voltage in the case of different gate–source voltages for the device with a 0.62 m gate length is investigated. Secondly, a comparison is made with the experimental report. Lastly, the transfer characteristic with different gate lengths and different buffer layers has been performed. The results show that the simulation is in accord with the experiment at the gate length of 0.62 m and the short channel effect becomes pronounced as gate length decreases. The E-mode will not be held below a100 nm gate length unless both transversal scaling and vertical scaling are being carried out simultaneously.

GeSi Source/Drain Structure for Suppression of Short Channel Effect in SOI p-MOSFET's

GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator （PDSOI） nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences （IMECAS）. Mechanisms determining short-channel effects （SCE） in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOI devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect （RSCE） than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.

A two-dimensional analytical model for channel potential and threshold voltage of short channel dual material gate lightly doped drain MOSFET

An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional（2D） analytical framework of triple material symmetrical gate stack（TMGS）DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS;device simulator to affirm and formalize the proposed device structure.

Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design

This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel.For the analysis,three different channel structures are used:(a)tri-layer stack channel(TLSC)(Si-SiGe-Si),(b)double layer stack channel(DLSC)(SiGe-Si),(c)single layer channel(SLC)(S_(i)).The I−V characteristics,subthreshold swing(SS),drain-induced barrier lowering(DIBL),threshold voltage(V_(t)),drain current(ION),OFF current(IOFF),and ON-OFF current ratio(ION/IOFF)are observed for the structures at a 20 nm gate length.It is seen that TLSC provides 21.3%and 14.3%more ON current than DLSC and SLC,respectively.The paper also explores the analog and RF factors such as input transconductance(g_(m)),output transconductance(gds),gain(gm/gds),transconductance generation factor(TGF),cut-off frequency(f_(T)),maximum oscillation frequency(f_(max)),gain frequency product(GFP)and linearity performance parameters such as second and third-order harmonics(g_(m2),g_(m3)),voltage intercept points(VIP_(2),VIP_(3))and 1-dB compression points for the three structures.The results show that the TLSC has a high analog performance due to more gm and provides 16.3%,48.4%more gain than SLC and DLSC,respectively and it also provides better linearity.All the results are obtained using the VisualTCAD tool.

基于购买漏斗模型的多渠道网络广告效应研究

从企业发起渠道(firm-initiated contacts,FICs)和客户发起渠道(customer-initiated contacts,CICs)两方面,探讨了不同网络广告的短期及长期效应。通过对网络广告短期效应和长期效应的综合测评,以期为企业营销合理分配广告预算提供实践指导。实证研究发现,从短期来看,FICs品牌型广告的即时效应最大,从长期来看,FICs广告有着最强的长期累积效应,特别是短信广告。FICs广告的效应持续时间比CICs广告的效应持续时间更长。CICs品牌型搜索广告在首页访问阶段产生了更高的效应,CICs通用型搜索广告在主页访问和详情页访问阶段的效应较为相近,而FICs广告能更有效地吸引客户转到特定的产品详情页面。

15 nm Bulk nFinFET器件性能研究及参数优化

为研究Bulk FinFET工作时基本结构参数、器件温度和栅极材料对其性能的影响,建立了一个15 nm n型Bulk FinFET器件模型,仿真分析了不同栅长、鳍宽、鳍高、沟道掺杂浓度、器件工作温度、栅极材料对器件性能的影响,发现增长栅长、降低鳍宽和增加鳍高有助于抑制短沟道效应;1×10^(17)cm^(-3)以下的低沟道掺杂浓度对器件特性影响不大,但高掺杂会使器件失效;器件工作温度的升高会导致器件性能的下降;采用高K介质材料作为栅极器件性能优于传统材料SiO_(2)。

集成侧墙技术的80nm栅GaN HEMT

目前业界主要采用电子束曝光技术制作高频氮化镓高电子迁移率晶体管(GaN HEMT)的深亚微米T型栅,存在效率低下、良率不足和成本较高的问题。本文采用集成侧墙技术,在6英寸工业化产线上首次成功制造了纯光学曝光的80 nm T型栅GaN HEMT,并对器件性能参数进行了全面表征和分析。器件单位栅宽(每毫米)下,最大输出电流Id,max为993 mA,峰值跨导Gm,peak为385 mS;阈值电压Uth为-3.25 V,关态击穿电压超过80 V;电流增益截止频率(fT)和功率增益截止频率(fmax)分别为64 GHz和175 GHz。在28 V工作时,器件在16 GHz下的饱和输出功率、功率增益和功率附加效率分别为26.95 dBm(每毫米4.9 W)、11.08 dB和49.78%;在30 GHz下器件的饱和输出功率、功率增益和功率附加效率分别为26.15 dBm(每毫米4.1 W)、8.8 dB和44%。结果表明,集成侧墙技术在深亚微米GaN HEMT制造中具备较好的应用前景。

渐变沟道全耗尽SOI MOSFET漏致势垒降低效应研究

目的 集SOI MOSFET(绝缘衬底上的硅金属氧化物半导体场效应晶体管)器件结构与渐变沟道的优点于一体,提出渐变沟道全耗尽SOI MOSFET器件结构,以提高MOSFET器件的微观物理性能。方法 分别列出沟道不同掺杂浓度的2个区域的泊松方程并求解,建立阈值电压模型。依据计算结果,详细分析沟道高掺杂区的掺杂浓度和掺杂长度、栅氧化层的介电常数、硅膜厚度等物理参数对漏致势垒降低(DIBL)效应的影响。结果 DIBL随沟道高掺杂区的掺杂浓度的增大而变小,随掺杂长度的减小而变小,随栅氧化层的介电常数的增大而变小,随硅层厚度减薄而变小。结论 渐变掺杂沟道结构能够有效抑制器件的DIBL。该研究结果不仅对器件的理论研究有一定的意义,而且对器件的设计提供了一定的参考价值。

短沟道负电容GAAFET的物理解析模型的理论推导

围栅场效应晶体管的EDA设计软件是我国芯片产业“卡脖子”的关键技术之一,已经受到科学界与产业界的高度重视.本文首先通过合理近似推导出传统短沟道GAAFE的物理解析模型,然后在此基础上通过增加铁电层推导出负电容GAAFET的物理解析模型.该物理模型的理论推导有助于加深学生对GAAFET工作原理的理解,激发学生的学习兴趣,提高学生的研究能力.

基于BSIM⁃CMG紧凑模型的NSFET直流特性建模

随着半导体制造工艺技术的发展,纳米片场效应晶体管(NSFET)成为下一代集成电路的核心器件,建立能准确描述NSFET特性的SPICE模型对提高基于NSFET的集成电路设计的成功率和缩短先进工艺的开发周期至关重要。结合Sentaurus TCAD仿真与伯克利短沟道绝缘栅场效应晶体管公共多栅(BSIM⁃CMG)紧凑模型,对NSFET进行直流特性建模。使用器件模型提取工具XModel提取器件的直流特性参数,包括单器件参数提取、温度及自热效应参数提取。结果表明,单器件直流特性参数提取平均误差小于5%,温度及自热效应的参数提取结果精准度较好,验证了模型的准确性。最后,构建并验证分组模型与工艺角模型。这些模型能准确描述不同尺寸和工艺波动对NSFET器件特性的影响,为加快高性能、低功耗NSFET的开发提供理论参考和实践指导。

Short-gate AlGaN/GaN high-electron mobility transistors with BGaN buffer

Using the semi-insulating property and small lattice constant a of wurtzite BGaN alloy, we propose a BGaN buffer with a B-content of 1% to enhance two-dimensional electron gas(2 DEG) confinement in a short-gate AlGaN/GaN highelectron mobility transistor(HEMT). Based on the two-dimensional TCAD simulation, the direct current(DC) and radio frequency(RF) characteristics of the AlGaN/GaN/B_(0.01)Ga_(0.99)N structure HEMTs are theoretically studied. Our results show that the BGaN buffer device achieves good pinch-off quality and improves RF performance compared with GaN buffer device. The BGaN buffer device can allow a good immunity to shift of threshold voltage for the aspect ratio(LG/d)down to 6, which is much lower than that the GaN buffer device with L_G/d=11 can reach. Furthermore, due to a similar manner of enhancing 2 DEG confinement, the B_(0.01)Ga_(0.99)N buffer device has similar DC and RF characteristics to those the AlGaN buffer device possesses, and its ability to control short-channel effects(SCEs) is comparable to that of an Al_(0.03)Ga_(0.97)N buffer. Therefore, this BGaN buffer with very small B-content promises to be a new method to suppress SCEs in GaN HEMTs.

Model and analysis of drain induced barrier lowering effect for 4H-SiC metal semiconductor field effect transistor

Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL （drain induced barrier lowering） effect for short channel 4H-SiC metal semiconductor field effect transistors （MESFETs）. An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H-SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a （channel length/channel depth） ratio, drain applied voltage VDS and channel doping concentration ND, thus providing a good basis for the design and modelling of short channel 4H-SiC MESFETs device.

10 nm金属氧化物半导体场效应晶体管中的热噪声特性分析

随着金属氧化物半导体场效应晶体管(MOSFET)器件等比例缩小至纳米级的较小尺寸,一方面导致的短沟道效应已严重影响热噪声;另一方面使栅、源、漏区及衬底区的热噪声占有比越来越高,而传统热噪声模型主要考虑较大尺寸器件的沟道热噪声,且其模型未考虑到沟道饱和区.本文针对小尺寸纳米级MOSFET器件,并根据器件结构特征和热噪声的基本特性,建立了10 nm器件的热噪声模型,该模型体现沟道区、衬底区及栅、源、漏区,同时考虑到沟道饱和区的热噪声.在模型的基础上,分析沟道热噪声、总热噪声随偏置参量及器件参数之间的关系,验证了沟道饱和区热噪声的存在,并与已有实验结果一致,所得结论有助于提高纳米级小尺寸MOSFET器件的工作效率、寿命及响应速度等.

UTBB SOI MOSFETs短沟道效应抑制技术

随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。

短期低频脉冲磁场诱导经典瞬时感受器电位通道1对肱二头肌最大自主收缩力与力量耐力的影响

背景:力量素质是人类进行身体活动的必备要素,短暂的低频脉冲磁场刺激可诱导和激活经典瞬时感受器电位通道1(classical transient receptor potential channel 1,TRPC1),并引发小鼠骨骼肌生长与重塑,从而对肌组织产生一系列生理支持效应,该机制是否会引发人体骨骼肌生理结构与工作能力的变化,并作为一种全新的人体肌力提升手段尚无研究。目的:选用可激活TRPC 1的特定低频脉冲磁场作为外源性刺激,以观察并验证短期刺激对人体肱二头肌最大自主收缩力与力量耐力的影响。方法:选择普通成年健康受试者27例,随机分为训练组、照射组、训练+照射组,每组9例。训练组采用抗阻训练,训练+照射组每次接受10 min低频脉冲磁场刺激(强度1.5 mT,频率3300 Hz)后即刻进行抗阻训练,照射组只进行10 min低频脉冲磁场刺激,试验周期9 d,间隔48 h进行1次训练或照射,为了观察低频脉冲磁场与抗阻训练结合是否会产生增益效果,训练组与训练+照射组在5次训练前后采集最大自主收缩力的肌电信息,照射组只在第1,3,5次进行最大自主收缩力测试,跟踪肌力变化情况。试验后观察3组受试最大自主收缩力值、1次重复最大力量、耐力持续时间、中值频率的变化。结果与结论:①在试验过程中,所有被试的最大自主收缩力值变化与时间交互效应显著(P<0.01),随时间的推进均出现显著变化,各组内最大自主收缩力值变化与时间交互显著(P<0.05),组间无交互效应;②各组被试后测最大自主收缩力值、1次重复最大力量、耐力持续时间、中值频率相比前测均显著提升,其中训练组各指标提升率依次为19%,23%,28%,18%,训练+照射组提升率依次为11%,10%,53%,18%,照射组各指标提升率依次为28%,18%,27%,6%;③训练+照射组的中值频率显著高于照射组(P<0.05),与训练组无显著性差异;④通过对训练组与训练+照射组每次训练前后的最大自主收缩力肌电均方根振幅平均值对比发现,训练组前2次训练后最大自主收缩力肌电均方根振幅平均值显著下降(P<0.05)。⑤结果证实:在强度1.5 mT,频率3300 Hz的脉冲磁场短期刺激方案下,人体肱二头肌最大自主收缩力值和力量耐力显著提升,低频脉冲磁场诱导TRPC1促进肌组织工作能力提升这一机制在人体上得到有效验证;在最大力量提升效果上,低频脉冲磁场刺激与该试验进行传统抗阻训练的两组最终力量水平一致;抗阻训练结合脉冲磁场刺激在训练过程中可体现出更好的抗疲劳能力,以及保持肌力稳定增长的功效,这种结合在训练初期可在相同负荷下使局部肌群更多的运动单位获得训练刺激,提升整体训练效率;在力量耐力提升效果上,低频脉冲磁场刺激可使肌肉等长收缩时间延长,抗疲劳能力提升,低频脉冲磁场刺激结合抗阻训练相比单纯进行低频脉冲磁场刺激可带来更加有效的力量耐力增益效果。

Simulation study on short channel double-gate junctionless field-effect transistors

We study the characteristics of short channel double-gate(DG) junctionless(JL) FETs by device simulation. OutputⅠ-Ⅴcharacteristic degradations such as an extremely reduced channel length induced subthreshold slope increase and the threshold voltage shift due to variations of body doping and channel length have been systematically analyzed.Distributions of electron concentration,electric field and potential in the body channel region are also analyzed.Comparisons with conventional inversion-mode(IM) FETs,which can demonstrate the advantages of JL FETs,have also been performed.

短期低频脉冲磁场诱导经典瞬时感受器电位通道1对局部肌肉肌力提升后的保持与衰减变化轨迹

背景:短暂的低频脉冲磁场刺激可诱导和激活经典瞬时感受器电位通道1,并可提升人体局部肌肉(如肱二头肌)的最大自主收缩力与力量耐力。目的:通过可激活经典瞬时感受器电位通道1的特定低频脉冲磁场作为肌力提升手段,并观察短期刺激对人体肱二头肌最大自主收缩力与力量耐力提升后的变化衰减过程。方法:选取普通成年健康受试者27例,随机等分为训练组、照射组、训练+照射组。训练+照射组每次接受10 min低频脉冲磁场刺激后即刻进行抗阻训练,照射组只进行10 min低频脉冲磁场刺激,训练组采用抗阻训练,试验时间为8周,在正式试验的第1-12天进行短期肌力提升方案及力量水平后测,随后6周观察各组最大自主收缩力与力量耐力的衰减变化过程。结果与结论:(1)所有被试者随着试验时间的不断推进,最大自主收缩力值变化显著(P <0.01),时间交互效应明显,组间无交互效应,时间与分组交互效应不显著。(2)与初测值相比,照射组肌力衰减最大自主收缩力跟踪的第1,2,3,4周均显著高于初测值;训练组肌力衰减最大自主收缩力跟踪的第1,4周均显著高于初测值;与后测值相比,照射组最大自主收缩力值肌力衰减跟踪的第5,6周显著低于后测值;训练组最大自主收缩力肌力衰减跟踪的第5,6周显著低于后测值;训练+照射组肌力衰减最大自主收缩力跟踪的第1,5,6周显著低于后测值。(3)通过对3组最大自主收缩力变化曲线进行相关性分析可以看出,照射组整体最大自主收缩力肌力变化与训练组及训练+照射组最大自主收缩力变化趋势高度正相关,变化趋势高度一致。与照射组相比,训练组与训练+照射组最大自主收缩力具有更强的正相关性。(4)各组被试随着时间的推进,中值频率值均发生显著性变化(P <0.01),时间交互效应明显,时间点和分组交互作用对中值频率值变化具有显著性影响(P <0.05)。(5)与初测值相比,照射组肌力衰减中值频率值跟踪的第2周显著高于初测值;训练+照射组所有肌力衰减中值频率值跟踪的第2周显著高于初测值;与后测值相比,照射组肌力衰减中值频率值跟踪均与后测无显著性差异;训练组肌力衰减中值频率值跟踪的第1,4周显著低于后测值;训练+照射组肌力衰减中值频率值跟踪的第1,2周显著低于后测值。(6)3组受试者力量耐力中值频率值变化曲线进行相关性分析可以看出,照射组与训练组和训练+照射组之间具备较低的正相关性,与训练组相比,训练+照射组与照射组之间的相关程度略高。(7)结果显示,在强度1.5 mT、频率3 300 Hz的脉冲磁场短期刺激方案使肌力增强后,最大自主收缩力衰减到初测值的周期为6周,与该试验抗阻训练的衰减周期及提升后的衰减速度一致,在衰减过程中相比进行抗阻训练的2组变化波动较小,无疲劳累积的影响,肌力保持水平较佳。力量耐力提升后至少可保持6周。相比抗阻训练的力量耐力变化,低频脉冲磁场刺激可免于疲劳累积的影响,抗疲劳能力持续增长与保持水平较好,抗阻训练结合脉冲磁场可观察到对耐力水平带来一定影响与增益效果,减少衰减过程的波动,利于耐力水平的保持。