The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17μm in thickness with 5 × 10...The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance (Ron,sv) is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V (IDS 〈 lOOnA) at VGS = 0 V.展开更多
Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal-oxide-semiconductor field-effect transistor ...Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal-oxide-semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.展开更多
In this paper the physical characteristics of FINFET (fin-field effect transistor) transistor behavior are investigated. For the analysis, semi-classical electron transfer method was used based on drift diffusion appr...In this paper the physical characteristics of FINFET (fin-field effect transistor) transistor behavior are investigated. For the analysis, semi-classical electron transfer method was used based on drift diffusion approximation by TCAD (Tiber CAD) software. Simulations show that the output resistance of FINFET along very small gate (gate length and fin height of 50 nm) is negative. The negative resistance is used in oscillators.展开更多
Two-dimensional(2D)semiconductors are attractive channels to shrink the scale of field-effect transistors(FETs),and among which the anisotropic one is more advantageous for a higher on-state current(I_(on)).Monolayer(...Two-dimensional(2D)semiconductors are attractive channels to shrink the scale of field-effect transistors(FETs),and among which the anisotropic one is more advantageous for a higher on-state current(I_(on)).Monolayer(ML)SnSe_(2),as an abundant,economic,nontoxic,and stable two-dimensional material,possesses an anisotropic electronic nature.Herein,we study the device performances of the ML SnSe_(2) metal-oxide-semiconductor FETs(MOSFETs)and deduce their performance limit to an ultrashort gate length(L_(g))and ultralow supply voltage(V_(dd))by using the ab initio quantum transport simulation.An ultrahigh I_(on) of 5,660 and 3,145µA/µm is acquired for the n-type 10-nm-L_(g) ML SnSe_(2) MOSFET at V_(dd)=0.7 V for high-performance(HP)and low-power(LP)applications,respectively.Specifically,until L_(g) scales down to 2 and 3 nm,the MOSFETs(at V_(dd)=0.65 V)surpass I_(on),intrinsic delay time(τ),and power-delay product(PDP)of the International Roadmap for Device and Systems(IRDS,2020 version)for HP and LP devices for the year 2028.Moreover,the 5-nm-L_(g) ML SnSe_(2) MOSFET(at V_(dd)=0.4 V)fulfills the IRDS HP device and the 7-nm-L_(g) MOSFET(at V_(dd)=0.55 V)fulfills the IRDS LP device for the year 2034.展开更多
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China under Grant No 2013ZX02305
文摘The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance (Ron,sv) is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V (IDS 〈 lOOnA) at VGS = 0 V.
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
基金Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203,9140A08060407DZ0103,and 6139801)
文摘Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal-oxide-semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.
文摘In this paper the physical characteristics of FINFET (fin-field effect transistor) transistor behavior are investigated. For the analysis, semi-classical electron transfer method was used based on drift diffusion approximation by TCAD (Tiber CAD) software. Simulations show that the output resistance of FINFET along very small gate (gate length and fin height of 50 nm) is negative. The negative resistance is used in oscillators.
基金the Beijing Natural Science Foundation of China(No.4212046)the National Natural Science Foundation of China(Nos.11704008 and 91964101)+1 种基金the Support Plan of Yuyou Youththe fund of high-level characteristic research direction from North China University of Technology.
文摘Two-dimensional(2D)semiconductors are attractive channels to shrink the scale of field-effect transistors(FETs),and among which the anisotropic one is more advantageous for a higher on-state current(I_(on)).Monolayer(ML)SnSe_(2),as an abundant,economic,nontoxic,and stable two-dimensional material,possesses an anisotropic electronic nature.Herein,we study the device performances of the ML SnSe_(2) metal-oxide-semiconductor FETs(MOSFETs)and deduce their performance limit to an ultrashort gate length(L_(g))and ultralow supply voltage(V_(dd))by using the ab initio quantum transport simulation.An ultrahigh I_(on) of 5,660 and 3,145µA/µm is acquired for the n-type 10-nm-L_(g) ML SnSe_(2) MOSFET at V_(dd)=0.7 V for high-performance(HP)and low-power(LP)applications,respectively.Specifically,until L_(g) scales down to 2 and 3 nm,the MOSFETs(at V_(dd)=0.65 V)surpass I_(on),intrinsic delay time(τ),and power-delay product(PDP)of the International Roadmap for Device and Systems(IRDS,2020 version)for HP and LP devices for the year 2028.Moreover,the 5-nm-L_(g) ML SnSe_(2) MOSFET(at V_(dd)=0.4 V)fulfills the IRDS HP device and the 7-nm-L_(g) MOSFET(at V_(dd)=0.55 V)fulfills the IRDS LP device for the year 2034.