Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate （DM-DG） strained Si （s-Si） metal-oxide semiconductor field effect transistors （MOSFETs） are presented. The surface potential and the surface electric field ex- pressions have been obtained by solving Poisson＇s equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate （SM-DG） MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.

SiC MOSFET和Si IGBT的结温特性及结温监测方法研究

为了研究结温对1 200 V SiC MOSFET和Si IGBT输出特性、漏电流、开关特性和器件损耗的影响,搭建了输出特性测试电路、漏电流测试电路和双脉冲测试电路,并针对SiC MOSFET和Si IGBT随结温变化的不同表现,提出了不同的结温监测方法。通过测试发现,SiC MOSFET和Si IGBT的导通压降和漏电流随结温升高而增大;Si IGBT的开通损耗和关断损耗均随结温升高而增大,而SiC MOSFET的开通损耗随结温升高先增大后减小,关断损耗随结温升高而增大;Si IGBT的开关时间随结温变化而单调变化,而SiC MOSFET的开关时间随结温变化没有明显的变化规律。

氮化感应致n-MOSFETsSi/SiO_2界面应力的研究

本文借助氩离子 (Ar+)背表面轰击技术研究不同氮化处理所导致的n MOSFETsSi/SiO2 界面附近剩余机械应力 .结果表明 :NH3氮化及N2 O生长的氧化物 硅界面附近均存在较大的剩余应力 ,前者来自过多的界面氮结合 ,后者来自因为初始加速生长阶段 .N2 O氮化的氧化物表现出小得多的剩余应力 。

采用低温Si技术的Si/SiGe异质结p-MOSFET

针对S i/S iG e p-M O SFET的虚拟S iG e衬底厚度较大(大于1μm)的问题,采用低温S i技术在S i缓冲层和虚拟S iG e衬底之间M BE生长低温-S i层。S iG e层应力通过低温-S i层释放,达到应变弛豫。XRD和AFM测试表明,S i0.8G e0.2层厚度可减薄至300 nm,其弛豫度大于85%,表面平均粗糙度仅为1.02 nm。试制出应变S i/S iG e p-M O SFET器件,最大空穴迁移率达到112 cm2/V s,其性能略优于目前多采用1μm厚虚拟S iG e衬底的器件。

半桥结构中的SiC MOSFET串扰电压建模研究

SiC MOSFET凭借着低开关损耗、高工作频率与高工作温度点等优点,逐渐在高效率、高功率密度与高温的应用场合取代传统的硅功率器件。然而,在高速开关中带来的栅极串扰现象严重制约SiC器件的开关速度。传统的串扰抑制方法重点关注由栅极–漏极寄生电容引入的干扰电压,往往通过减小驱动回路阻抗的方式来降低串扰电压。该文基于SiC MOSFET器件的开关模态,提出考虑共源电感的分段线性化串扰电压模型。该模型基于器件数据手册及双脉冲实验提取的参数,考虑栅极–漏极电容、共源电感、体二极管反向恢复等非理想因素的影响。对比不同电压点、电流点与电阻值下实验与模型的输出结果。该模型表明,串扰电压是由器件栅极–漏极电容、共源电感与驱动回路阻抗共同作用的结果。单一降低驱动回路阻抗的方式对串扰电压的抑制效果有限。基于提出的模型,该文给出串扰电压抑制的指导方法,可直接用于SiC MOSFET驱动电路的设计。

超深亚微米n沟道Si-MOSFET中栅介质的击穿

通过改变Si-MOSFET的栅电压、源电压、漏电压和栅氧化层厚度等参数,分析和求解栅介质下载流子迁移率、沟道内电流密度、电场、雪崩产生密度以及隧穿电流的变化,得出当源、漏偏压分别为0.5V和1.0V时,增大栅极电压到18V时,栅氧化层(3nm)被永久性击穿;而在栅、源、漏偏压分别为5V、0.5V、1.0V不变时,减薄栅氧化层到0.335nm时,栅氧化层被永久性击穿。

考虑器件工作温度影响的Si C功率MOSFET建模

提出一种基于MATLAB/Simulink的SiC功率MOSFET全工作区变温度参数建模方法。在Si基横向双扩散MOSFET模型的基础上,采用与温度相关的电流源和电压源补偿器件漏极电流和阈值电压的变化。通过补充实验拓展SiC功率MOSFET的饱和区工作特性曲线,并根据Si C功率MOSFET的工作特性,采用数学拟合的方法来提取模型参数。在保留各个参数物理意义的同时,摆脱建模过程对物理参数的依赖。在不同电压、电流及温度(25~200℃)的情况下对器件的输出特性、转移特性、阈值电压、导通电阻及开关损耗进行测试,将测试结果与MATLAB/Simulink模型仿真结果进行性比较。模型仿真结果与实际测试结果一致,开关损耗误差在7%之内,验证了模型的准确性及有效性,为实际应用Si C功率MOSFET时系统性能及损耗分析提供参考依据。

Si IGBT/SiC MOSFET混合器件及其应用研究

综述了Si IGBT/SiC MOSFET混合器件在门极优化控制策略、集成驱动设计、热电耦合损耗模型、芯片尺寸配比优化和混合功率模块研制等方面的最新研究成果与进展。Si IGBT/SiC MOSFET混合器件结合了SiC MOSFET的高开关频率、低开关损耗特性和Si IGBT的大载流能力和低成本优势,已有文献的最新研究和实验结果验证了该类器件的优异特性,表明其对高性能电力电子器件实现更高电流容量、更高开关频率和较低成本具有重要意义,是高性能变换器应用中非常有潜力的功率器件类型。

SiC MOSFET与Si IGBT器件温度敏感电参数对比研究

功率半导体器件结温是反映器件健康状态的关键指标。目前被认为具有前景的在线实时结温提取方案是基于器件本身的温度敏感电参数TSEPs(temperature sensitive electrical parameters)法,对于Si IGBT器件温敏电参数的在线实时结温提取方法国内外已有大量文献报道,但对于宽禁带SiC器件研究甚少,且对于不同种温敏电参数的特性差异分析极为必要。因此,提出针对不同温敏电参数在SiC MOSFET和Si IGBT上的对比分析。首先对SiC MOSFET的静态和动态温敏电参数进行理论建模分析获取结温敏感依据,后续通过实验多维度对比分析温敏电参数在SiC MOSFET和Si IGBT的适用性。最后就各温敏电参数的提取电路设计进行分析对比。实验结果表明,通态电阻Ron和开通di/dt更适合于SiC MOSFET,而VTH、td-off和VGP更适合于Si IGBT。

基于Si和SiC器件的混合型级联多电平变换器及其调控优化方法

针对现有级联型多电平变换器器件多、损耗大、功率密度低等问题,该文提出一种基于Si和SiC器件的混合型级联多电平变换器(HCMC)拓扑结构。HCMC由全Si IGBT器件的中性点钳位(NPC)型三电平单元与由SiIGBT、SiCMOSFET器件混合的级联H桥(CHB)单元串联构成。针对此拓扑提出一种特定的高低频混合调制策略,充分发挥SiC MOSFET开关损耗低、SiIGBT通态损耗低的优势,并对NPC单元直流侧电压和CHB单元子模块数进行优化设计。此外,为解决子模块电容电压不平衡问题,提出一种轮换均压控制策略。最后,在6kV系统无功补偿工况下进行仿真和实验,验证了HCMC拓扑结构和调制策略的可行性,并将HCMC和现有级联型多电平变换器进行综合对比,证明了所提拓扑在保证输出性能的条件下大大降低了运行损耗。

基于SiC MOSFET/Si IGBT的670V/100kW城轨辅助逆变器的综合比较

三相全桥逆变器广泛应用于各个领域,特别是轨道交通的牵引变流器系统和辅助变流器系统。利用新一代功率半导体器件如碳化硅(SiC)提升功率密度,使三相逆变器向小型化、轻量化的方向发展。采用SiC MOSFET以减小主回路电感的设计为优化目标,研制了用于城轨辅助变流的新型逆变器样机,与原有的Si IGBT逆变器进行了结构与电气性能的对比。理论分析和试验测试的结果表明,该逆变器样机的最大输出功率可达132 kW,此时逆变器样机的功率密度相应为1.49 kW/dm^(3)或3.64 kW/kg。

非分段GaN HEMT EF2类功率放大器理论研究

目前,增强型氮化镓高电子迁移率晶体管(GaN HEMT)的仿真模型存在仿真时间长、复杂度高且收敛性不好等问题。为了解决GaN HEMT器件在电力电子电路中仿真收敛性和准确性差的问题,提出一种非分段的GaN HEMT SPICE模型。使用非分段连续方程对GaN HEMT器件的静态和动态特性进行建模;再对GaN HEMT的输出特性进行仿真,并与Si MOSFET的仿真结果进行对比。仿真结果表明,所提模型的收敛性较好,收敛速度快,有较高的准确性。另外,将此模型应用于EF2类功率放大器中,研究该模型对传输效率的影响。仿真结果进一步表明:该模型具有良好的收敛性;且当开关频率为10~20 MHz,输入功率为75 W时,输出功率可达73 W,传输效率为95%,这也证明了GaN HEMT器件可以提高EF2类功率放大器的传输效率。

基于Si IGBT和SiC MOSFET的飞跨电容MMC拓扑及其调制策略

降低模块化多电平变换器(modular multilevel converter,MMC)子模块电容电压波动对提高MMC功率密度,实现MMC轻型化具有重要意义。在降低MMC子模块电容电压波动的方案中,飞跨电容MMC(flying-capacitor MMC,FC-MMC)以其良好的性能得到了广泛的关注。基于传统FC-MMC方案,提出了一种采用Si IGBT与SiC MOSFET混合器件的FC-MMC拓扑,该拓扑每个桥臂包括两个SiC子模块及多个Si子模块,减少了SiC功率器件的使用量。进而提出了相应的调制策略,将大部分开关动作转移到SiC子模块,充分利用了SiC MOSFET开关损耗低和Si IGBT导通损耗低的优势,在不过多增加成本的情况下,降低了FC-MMC的总损耗。通过实验和损耗分析验证了所提方案的有效性和可行性。

SiC MOSFET功率器件标准研究

本文结合SiC MOSFET国际标准进展,分析了阈值电压漂移、偏压温度不稳定性、体二极管退化测试标准的制定难点;同时,根据国内外产业发展现状、我国技术标准进展,分析了测试设备精度、新型封装、动态可靠性等关键问题与标准制定面临的挑战,并提出了首先定位团体标准制定的工作机制,以期以技术标准的研制支撑产业的市场化发展。

The study on two-dimensional analytical model for gate stack fully depleted strained Si on silicon-germanium-on-insulator MOSFETs

Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.

A two-dimensional subthreshold current model for strained-Si MOSFET

An analytical model for the subthreshold current of a strained-Si metal-oxide-semiconductor field-effect transistor (MOSFET) is developed by solving the two-dimensional (2D) Poisson equation and the conventional drift-diffusion theory. Model verification is carried out using the 2D device simulator ISE. Good agreement is obtained between the model's calculations and the simulated results. By analyzing the model, the dependence of current on the strained-Si layer strain, doping concentration, source/drain junction depths and substrate voltage is studied. This subthreshold current model provides valuable information for strained-Si MOSFET design.

Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson＇s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor （CMOS）-based device in a nanoscale regime.

Two-dimensional analytical models for asymmetric fully depleted double-gate strained silicon MOSFETs

This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.

A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs

On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.

SiC MOSFET及Si IGBT串联短路动态特性研究

针对因器件击穿、控制失效等问题导致的串联短路现象,基于半桥结构分析了SiC MOSFET及Si IGBT不同的串联短路动态分压特性。同时,结合开关过程中电压、电流的变化分析串联短路分压原理,并在输出特性曲线上标注器件的分压路径。实验结果表明,驱动电压、负载电流、母线电压等外部驱动参数对两种器件串联短路分压特性的影响不同,其中反向负载电流改变了串联短路的分压趋势且对串联短路特性影响最大。充分认识器件的串联短路机理对改进短路保护具有现实意义。