A SiC asymmetric cell trench MOSFET with a split gate and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode

A new SiC asymmetric cell trench metal–oxide–semiconductor field effect transistor(MOSFET)with a split gate(SG)and integrated p^(+)-poly Si/SiC heterojunction freewheeling diode(SGHJD-TMOS)is investigated in this article.The SG structure of the SGHJD-TMOS structure can effectively reduce the gate-drain capacitance and reduce the high gateoxide electric field.The integrated p^(+)-poly Si/SiC heterojunction freewheeling diode substantially improves body diode characteristics and reduces switching losses without degrading the static characteristics of the device.Numerical analysis results show that,compared with the conventional asymmetric cell trench MOSFET(CA-TMOS),the high-frequency figure of merit(HF-FOM,R_(on,sp)×Q_(gd,sp))is reduced by 92.5%,and the gate-oxide electric field is reduced by 75%.In addition,the forward conduction voltage drop(V_(F))and gate-drain charge(Q_(gd))are reduced from 2.90 V and 63.5μC/cm^(2) in the CA-TMOS to 1.80 V and 26.1μC/cm^(2) in the SGHJD-TMOS,respectively.Compared with the CA-TMOS,the turn-on loss(E_(on)) and turn-off loss(E_(off)) of the SGHJD-TMOS are reduced by 21.1%and 12.2%,respectively.

Novel Si/SiC heterojunction lateral double-diffused metal-oxide semiconductor field-effect transistor with p-type buried layer breaking silicon limit

A novel silicon carbide(SiC) on silicon(Si) heterojunction lateral double-diffused metal-oxide semiconductor fieldeffect transistor with p-type buried layer(PBL Si/SiC LDMOS) is proposed in this paper for the first time.The heterojunction has breakdown point transfer(BPT) characteristics,and the BPT terminal technology is used to increase the breakdown voltage(BV) of Si/SiC LDMOS with the deep drain region.In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region,the p-type buried layer is introduced in PBL Si/SiC LDMOS.The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer,which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance(R_(on,sp)).Through TCAD simulation,when the drift region length is 20 μm,the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS,increased by 77%;And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure,increased by 15%.The figure-of-merit(FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm^(2) and 6.37 MW/cm^(2),respectively.For the PBL Si/SiC LDMOS with the drift length of 20 μm,the maximum FOM is 6.86 MW/cm^(2).The PBL Si/SiC LDMOS breaks conventional silicon limit.

SiC based Si/SiC heterojunction and its rectifying characteristics

The Si on SiC heterojunction is still poorly understood, although it has a number of potential applications in electronic and optoelectronic devices, for example, light-activated SiC power switches where Si may play the role of an light absorbing layer. This paper reports on Si films heteroepitaxially grown on the Si face of （0001） n-type 6H-SiC substrates and the use of B2H6 as a dopant for p-Si grown at temperatures in a range of 700-950℃. X-ray diffraction （XRD） analysis and transmission electron microscopy （TEM） tests have demonstrated that the samples prepared at the temperatures ranged from 850℃ to 900℃ are characterized as monocrystalline silicon. The rocking XRD curves show a well symmetry with FWHM of 0.4339° Omega. Twin crystals and stacking faults observed in the epitaxial layers might be responsible for widening of the rocking curves. Dependence of the crystal structure and surface topography on growth temperature is discussed based on the experimental results. The energy band structure and rectifying characteristics of the Si/SiC heterojunctions are also preliminarily tested.

低压Si MOSFETs对SiC/Si级联器件短路特性的影响

由低压硅金属-氧化物-半导体场效应晶体管(Silicon Metal-Oxide-Semiconductor Field-Effect Transistor, Si MOSFET)和碳化硅结型场效应晶体管(Silicon Carbon Junction Field-Effect Transistor, SiC JFET)构成的SiC/Si级联(Cascode)器件,兼具了低压Si MOSFET易于驱动、SiC JFET高耐压低损耗等优点。该文采用实验和数值模拟的方式研究了低压Si MOSFET对SiC/Si级联器件短路特性的影响,结果表明,在短路过程中SiC/Si级联器件中的SiC JFET最高温度比单独的SiC JFET短路时的最高温度低,SiC/Si级联器件的短路失效时间得到了延长,并且随着Si MOSFET额定电压的增加,SiC/Si级联器件短路失效延长的时间也在增加。

基于热网络分区等效策略的Si/SiC混合器件耦合热参数辨识方法

由硅(Si)绝缘栅双极型晶体管(IGBT)与碳化硅(SiC)金属氧化物半导体场效应晶体管(MOSFET)并联构成的混合器件可打破单一Si基器件和SiC基器件的局限性,实现损耗和成本间的有效均衡。结温估计对于Si/SiC混合器件的可靠运行至关重要,然而,目前针对热监测的研究往往需满足热稳态平衡和功率损耗可测两大条件,在实际变流器中实用性较低。基于此,该文以零输入响应法为切入点,首先,对Si/SiC混合器件热结构特性进行分析,详细阐述零输入响应法直接应用于混合器件时所带来的高阶热约束条件难以表征的问题;其次,通过对SiIGBT与SiC MOSFET进行热网络分区处理实现模型的降阶,构建出壳温降温曲线时间常数与热参数之间的约束关系,提出了基于热网络分区等效思想的混合器件耦合热参数辨识方法,所提方法简化了功率损耗测量步骤与热平衡态条件,在并联器件耦合热参数辨识研究中具有简单、通用、流程化高的应用优势;最后,通过实验验证了该文所提方法的准确性和有效性。

硅基SiC薄膜制备与应用研究进展

碳化硅(SiC)材料具有极为优良的物理、化学及电学性能,可满足在高温、高腐蚀等极端条件下的应用,碳化硅还是极端工作条件下微机电系统(MEMS)的主要候选材料,成为国际上新材料、微电子和光电子领域研究的热点。同时,碳化硅有与硅同属立方晶系的同质异形体,可与硅工艺技术相结合制备出适应大规模集成电路需要的硅基器件,因此用硅晶片作为衬底制备碳化硅薄膜的工作受到研究人员的特别重视。本文综述了近年来国内外硅基碳化硅薄膜的研究现状,就其制备方法进行了系统的介绍,主要包括各种化学气相沉积(Chemical vapor deposition,CVD)法和物理气相沉积(Physical vapor deposition,PVD)法,并归纳了对硅基碳化硅薄膜性能的研究,包括杨氏模量、硬度、薄膜反射率、透射率、发光性能、电阻、压阻、电阻率和电导率等,以及其在微机电系统传感器、生物传感器和太阳能电池等领域的应用,最后对硅基碳化硅薄膜未来的发展进行了展望。

Interfacial photoconductivity effect of type-Ⅰ and type-Ⅱ Sb2Se3/Si heterojunctions for THz wave modulation

An in-depth understanding of the photoconductivity and photocarrier density at the interface is of great significance for improving the performance of optoelectronic devices. However, extraction of the photoconductivity and photocarrier density at the heterojunction interface remains elusive. Herein, we have obtained the photoconductivity and photocarrier density of 173 nm Sb2Se3/Si(type-Ⅰ heterojunction) and 90 nm Sb2Se3/Si(type-Ⅱ heterojunction) utilizing terahertz(THz) time-domain spectroscopy(THz-TDS) and a theoretical Drude model. Since type-Ⅰ heterojunctions accelerate carrier recombination and type-Ⅱ heterojunctions accelerate carrier separation, the photoconductivity and photocarrier density of the type-Ⅱ heterojunction(21.8×10^(4)S·m^(-1),1.5 × 10^(15)cm^(-3)) are higher than those of the type-Ⅰ heterojunction(11.8×10^(4)S·m^(-1),0.8×10^(15)cm^(-3)). These results demonstrate that a type-Ⅱ heterojunction is superior to a type-Ⅰ heterojunction for THz wave modulation. This work highlights THz-TDS as an effective tool for studying photoconductivity and photocarrier density at the heterojunction interface. In turn, the intriguing interfacial photoconductivity effect provides a way to improve the THz wave modulation performance.

A 3D SiC MOSFET with poly-silicon/SiC heterojunction diode

A three-dimensional(3D)silicon-carbide(SiC)trench metal-oxide-semiconductor field-effect transistor(MOSFET)with a heterojunction diode(HJD-TMOS)is proposed and studied in this work.The SiC MOSFET is characterized by an HJD which is partially embedded on one side of the gate.When the device is in the turn-on state,the body parasitic diode can be effectively controlled by the embedded HJD,the switching loss thus decreases for the device.Moreover,a highly-doped P+layer is encircled the gate oxide on the same side as the HJD and under the gate oxide,which is used to lighten the electric field concentration and improve the reliability of gate oxide layer.Physical mechanism for the HJD-TMOS is analyzed.Comparing with the conventional device with the same level of on-resistance,the breakdown voltage of the HJD-TMOS is improved by 23.4%,and the miller charge and the switching loss decrease by 43.2%and 48.6%,respectively.

a-Si/c-Si heterojunction solar cells on SiSiC ceramic substrates

Silicon thin-film solar cells are considered to be one of the most promising cells in the future for their potential advantages, such as low cost, high efficiency, great stability, simple processing, and none-pollution. In this paper, latest progress on poly-crystalline silicon solar cells on ceramic substrates achieved by our group was reported. Rapid thermal chemical vapor deposition (RTCVD) was used to deposited poly-crystalline silicon thin films, and the grains of as-grown film were enlarged by Zone-melting Recrystallization (ZMR). As a great change in cell′s structure, traditional diffused pn homojunction was replaced by a-Si/c-Si heterojunction, which lead is to distinct improvement in cell′s efficiency. A conversion efficiency of 3.42% has been achieved on 1 cm2 a-Si/c-Si heterojunction solar cell (Isc=16.93 mA, Voc=310.9 mV, FF=0.6493, AM=1.5 G, 24 ℃), while the cell with diffused homojunction only got an efficiency of 0.6%. It indicates that a-Si emitter formed at low temperature might be more suitable for thin film cell on ceramics.

基于Si和SiC器件的混合型级联多电平变换器及其调控优化方法

针对现有级联型多电平变换器器件多、损耗大、功率密度低等问题,该文提出一种基于Si和SiC器件的混合型级联多电平变换器(HCMC)拓扑结构。HCMC由全Si IGBT器件的中性点钳位(NPC)型三电平单元与由SiIGBT、SiCMOSFET器件混合的级联H桥(CHB)单元串联构成。针对此拓扑提出一种特定的高低频混合调制策略,充分发挥SiC MOSFET开关损耗低、SiIGBT通态损耗低的优势,并对NPC单元直流侧电压和CHB单元子模块数进行优化设计。此外,为解决子模块电容电压不平衡问题,提出一种轮换均压控制策略。最后,在6kV系统无功补偿工况下进行仿真和实验,验证了HCMC拓扑结构和调制策略的可行性,并将HCMC和现有级联型多电平变换器进行综合对比,证明了所提拓扑在保证输出性能的条件下大大降低了运行损耗。

具有异质结体二极管和N包围型P柱的4H-SiC超结MOSFET

利用TCAD仿真研究了一种具有异质结体二极管与N包围型P柱超结的4H-SiC UMOSFET(SJH-MOSFET)。通过在SJH-MOSFET中引入异质结和具有电荷平衡的超结结构,能够有效地优化器件的击穿电压、比导通电阻、反向恢复特性。研究结果表明,薄轻掺杂的电流扩展层(CSL)和N型包围使得耗尽区变窄,并为电流的流动提供了两个扩散路径,其中CSL使得电子快速地水平扩散,而N型包围允许电子可以垂直地流动,改进后结构的耐压提升了13.6%,栅槽底部高电场降低了10.5%,比导通电阻降低了10.5%,开启时间降低了38.4%,关断时间降低了44.7%;体区嵌入P+多晶硅与漂移区接触形成异质结体二极管,由于异质结特殊的能带结构,使得体二极管在导通时,P+多晶硅里空穴较少地流入到漂移区,使反向恢复电荷降低了42.96%,反向恢复时间降低了4.17%。

Si/SiC超结LDMOSFET的短路和温度特性

Si/SiC超结横向双扩散金属氧化物半导体场效应管(SJ-LDMOSFET)能有效改善Si SJ-LDMOSFET阻断电压低、温度特性差和短路可靠性低的问题。采用TCAD软件对Si SJ-LDMOSFET和Si/SiC SJ-LDMOSFET的短路和温度特性进行研究。当环境温度从300 K上升到400 K时,Si/SiC SJ-LDMOSFET内部最高温度均低于Si SJ-LDMOSFET,表现出良好的抑制自热效应的能力;Si/SiC SJ-LDMOSFET的击穿电压基本保持不变,且饱和电流退化率较低。发生短路时,Si/SiC SJ-LDMOSFET内部最高温度上升率要明显小于Si SJ-LDMOSFET。在环境温度为300 K和400 K时,Si/SiC SJ-LDMOSFET的短路维持时间相对于Si SJ-LDMOSFET分别增加了230%和266.7%。研究结果显示Si/SiC SJ-LDMOSFET在高温下具有更好的温度稳定性和抗短路能力,适用于高温、高压和高短路可靠性要求的环境中。

SiC/Si-Mo-Cr涂层SiC_(f)/SiC复合材料辐照行为

通过浆料涂刷法(Slurry painting,SP)结合化学气相沉积(Chemical vapor deposition,CVD),在SiC_(f)/SiC复合材料表面制备了致密的SiC/Si-Mo-Cr复合涂层。采用拉曼光谱、XRD和SEM研究了Si^(2+)离子辐照前后涂层的相组成、结构和形貌,并通过三点弯曲试验评估了辐照前后涂层样品的力学性能。结果表明:SiC_(f)/SiC复合材料在Si^(2+)离子辐照后发生结构损伤,如SiC纤维变得更粗糙,PyC界面膨胀以及SiC基体非晶化;而制备好的涂层可以极大地保护SiCf/SiC复合材料;因此,内部的纤维、界面和SiC基体在Si^(2+)离子辐照中都没有出现损伤。辐照后,SiC_(f)/SiC复合材料在辐照损伤区的界面脱黏和纤维拔出减少,弯曲断口变平,力学性能下降,弯曲强度保持率为80.49%;与之相比,涂层样品在辐照后的弯曲强度保持率更高,达到84.15%。

高体分SiCp/Al复合材料的热加工特性研究

利用Gleeble-1500型热模拟试验机,在变形温度420~540℃、应变速率0.003~0.100 s-1的条件下对真空热压法制备的25vol%SiCp/Al-30Si复合材料进行了等温热压缩试验,建立了基于峰值应力的包含Arrhenius项同时考虑应变、应变速率及温度影响的本构方程,观察了复合材料压缩变形前后的组织形貌。结果表明:25vol%SiCp/Al-30Si复合材料的流变应力随变形温度的升高而降低,随应变速率的增加而升高,显示为较强的变形温度与应变速度敏感性。通过线性回归分析计算了复合材料的应变指数n以及变形激活能Q,复合材料的热压缩流变应力可用包含Zener-Hollomon参数的双曲线正弦关系来描述。复合材料在低温热压缩变形中发生了伪塑性变形,温度不低于540℃、应变速率0.003~0.010 s-1条件下热加工可修复和改善复合材料的空洞和颗粒区域性分布不均。

Si/SiC混合开关最优门极延时及其在逆变器中的应用

由大电流硅绝缘栅双极型晶体管(Silicon Insulated-Gate Bipolar Transistor,Si IGBT)和小电流碳化硅金属-氧化物-半导体场效应晶体管(Silicon Carbon Metal-Oxide-Semiconductor Field-Effect Transistor,SiC MOSFET)并联构成的Si/SiC混合开关具有低成本、高效率的特点. Si/SiC混合开关门极关断延时的控制是提高混合开关效率的关键因素.本文首先研究了在不同工作电流下Si/SiC混合开关关断损耗随门极关断延时的变化,结果表明,Si/SiC混合开关有一个最优的关断延时,此时混合开关的关断损耗最低,并且最优门极关断延时随混合开关工作电流的增大而减小.将所得到的Si/SiC混合开关最优门极关断延时应用在单相全桥逆变器中,实验结果表明,逆变器的转换效率比同等条件下固定关断延时的最高转换效率提高了0.67%.

High‑Quality Epitaxial N Doped Graphene on SiC with Tunable Interfacial Interactions via Electron/Ion Bridges for Stable Lithium‑Ion Storage

Tailoring the interfacial interaction in SiCbased anode materials is crucial to the accomplishment of higher energy capacities and longer cycle lives for lithium-ion storage.In this paper,atomic-scale tunable interfacial interaction is achieved by epitaxial growth of high-quality N doped graphene(NG)on SiC(NG@SiC).This well-designed NG@SiC heterojunction demonstrates an intrinsic electric field with intensive interfacial interaction,making it an ideal prototype to thoroughly understand the configurations of electron/ion bridges and the mechanisms of interatomic electron migration.Both density functional theory(DFT)analysis and electrochemical kinetic analysis reveal that these intriguing electron/ion bridges can control and tailor the interfacial interaction via the interfacial coupled chemical bonds,enhancing the interfacial charge transfer kinetics and preventing pulverization/aggregation.As a proof-of-concept study,this well-designed NG@SiC anode shows good reversible capacity(1197.5 mAh g^(−1)after 200 cycles at 0.1 A g^(−1))and cycling durability with 76.6%capacity retention at 447.8 mAh g^(−1)after 1000 cycles at 10.0 A g^(−1).As expected,the lithium-ion full cell(LiFePO_(4)/C//NG@SiC)shows superior rate capability and cycling stability.This interfacial interaction tailoring strategy via epitaxial growth method provides new opportunities for traditional SiC-based anodes to achieve high-performance lithium-ion storage and beyond.

Si/SiC混合并联功率器件开关模式优化及特性分析

在对比SiC MOSFET和Si IGBT器件开关特性的基础上,提出了一种SiC MOSFET和Si IGBT混合并联器件的优化开关模式,并结合系统稳态模型,分析了其非理想开关过程特性。利用双脉冲测试,对不同开通/延迟时间下的混合并联器件开关特性展开了实验。实验结果表明,所提开关模式能够同步实现SiC MOSFET扩容并降低Si IGBT的开关损耗。该研究成果可对拓展两种开关器件的混合应用提供技术参考。

聚焦离子束在二维多孔Si/Al_(2)O_(3)/SiC薄膜透射电镜截面微观结构表征中的应用

二维多孔Si/Al_(2)O_(3)/SiC薄膜材料的透射电镜截面微观结构表征中,存在薄膜易脱落、脆性大、耐磨性差,以及选区制备难度大、制样效率低、成功率低等问题。采用聚焦离子束技术,成功地进行了二维多孔Si/Al_(2)O_(3)/SiC薄膜的透射电镜截面微观形貌的表征。结果表明,聚焦离子束技术是一种可以有效减少二维多孔薄膜样品制备过程中的损伤,进行高质量进行透射电镜截面微观结构表征的方法。

Indium–tin oxide films obtained by DC magnetron sputtering for improved Si heterojunction solar cell applications

The indium-tin oxide （ITO） film as the antireflection layer and front electrodes is of key importance to obtaining high efficiency Si heterojunction （HJ） solar cells. To obtain high transmittance and low resistivity ITO films by direct-current （DC） magnetron sputtering, we studied the impacts of the ITO film deposition conditions, such as the oxygen flow rate, pressure, and sputter power, on the electrical and optical properties of the ITO films. ITO films of resistivity of 4 x 10-4 ~.m and average transmittance of 89% in the wavelength range of 380-780 nm were obtained under the optimized conditions： oxygen flow rate of 0.1 sccm, pressure of 0.8 Pa, and sputtering power of 110 W. These ITO films were used to fabricate the single-side HJ solar cell without an intrinsic a-Si：H layer. However, the best HJ solar cell was fabricated with a lower sputtering power of 95 W, which had an efficiency of 11.47%, an open circuit voltage （Voc） of 0.626 V, a filling factor （FF） of 0.50, and a short circuit current density （Jsc） of 36.4 mA/cm2. The decrease in the performance of the solar cell fabricated with high sputtering power of 110 W is attributed to the ion bombardment to the emitter. The Voc was improved to 0.673 V when a 5 nm thick intrinsic a-Si：H layer was inserted between the （p） a-Si：H and （n） c-Si layer. The higher Voc of 0.673 V for the single-side HJ solar cell implies the excellent c-Si surface passivation by a-Si：H.

石墨表面Si-SiC-TaB_(2)抗烧蚀复合涂层的制备及性能研究

为了提高碳材料的抗烧蚀性能,以石墨块作为基体,SiC(d50=10μm)、B4C(d50=50μm)、TaC(d50=3μm)为主要原料,采用料浆法结合反应熔渗Si在石墨材料表面制备了Si-SiC和Si-SiC-TaB_(2)涂层,研究了涂层的物相组成、显微结构和元素分布,考察了Si-SiC-TaB_(2)复合涂层在室温至1600℃的抗热震性能,并通过等离子火焰烧蚀试验(2350℃分别烧蚀120和1980 s)测试了涂层对石墨材料高温下的抗烧蚀防护性能。结果表明:Si-SiC-TaB_(2)复合涂层结构致密,涂层中SiC和TaB_(2)陶瓷颗粒与Si无明显界面;在1600℃热震循环20次后,涂层试样的质量基本逐渐增加,具有良好的抗热震性能;Si-SiC-TaB_(2)复合涂层试样烧蚀1980 s后质量增加,表面覆盖了含有Ta_(2)O_(5)和SiO^(2)的Ta-Si-O氧化保护层,有效防止了高温火焰对石墨内部的侵蚀。Si-SiC涂层试样烧蚀后质量减少,表面形成了破损的SiO_(2)氧化层,出现了清晰可见的烧蚀凹坑。