Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characte...Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characterize and analyze the ML structures.The high resolution transmission electron microscopy(HRTEM)results show that the ML structure with 20 nm Si_(0.7)Ge_(0.3)features the best crystal quality and no defects are observed.Stacked Si_(0.7)Ge_(0.3)ML structures etched by three different methods were carried out and compared,and the results show that they have different selectivities and morphologies.In this work,the fabrication process influences on Si/Si Ge MLs are studied and there are no significant effects on the Si layers,which are the channels in lateral gate all around field effect transistor(L-GAAFET)devices.For vertically-stacked dynamic random access memory(VS-DRAM),it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness.These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires,nanosheet L-GAAFETs,and DRAM devices.展开更多
The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentrati...The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.展开更多
Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer i...Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.展开更多
基金supported in part by the Strategic Priority Research Program of the Chinese Academy of Sciences (Project ID.XDA0330300)in part by Innovation Program for Quantum Science and Technology (Project ID.2021ZD0302301)in part by the Youth Innovation Promotion Association of CAS (Project ID.2020037)。
文摘Fifteen periods of Si/Si_(0.7)Ge_(0.3)multilayers(MLs)with various Si Ge thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition(RPCVD).Several methods were utilized to characterize and analyze the ML structures.The high resolution transmission electron microscopy(HRTEM)results show that the ML structure with 20 nm Si_(0.7)Ge_(0.3)features the best crystal quality and no defects are observed.Stacked Si_(0.7)Ge_(0.3)ML structures etched by three different methods were carried out and compared,and the results show that they have different selectivities and morphologies.In this work,the fabrication process influences on Si/Si Ge MLs are studied and there are no significant effects on the Si layers,which are the channels in lateral gate all around field effect transistor(L-GAAFET)devices.For vertically-stacked dynamic random access memory(VS-DRAM),it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness.These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires,nanosheet L-GAAFETs,and DRAM devices.
文摘The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.
文摘Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.
