In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 ...In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 V due to the formation of Er oxide. Moreover, it is observed that the equivalent oxide thickness is thinned down by 0.5 nm because the thickness of interfacial layer is significantly reduced, which is thought to be attributed to the strong binding capability of the implanted Er atoms with oxygen atoms. In addition, cross-sectional transmission electron microscopy experiment shows that the HfO2 layer with Er ion implantation is still amorphous after annealing at a high temperature. This Er ion implantation technique has the potential to be implemented as a band edge metal gate solution for NMOS without a capping layer, and may also satisfy the demand of the EOT reduction in 32 nm technology node.展开更多
基金supported by the State Key Development Program for Basic Research of China(Grant No. 2011CBA00602)the National Natural Science Foundation of China(Grant Nos. 60876076 and 60976013)
文摘In this paper, we report the fabrication, electrical and physical characteristics of TiN/HfO2/Si MOS capacitors with erbium （Er） ion implantation. It is demonstrated that the fiat band voltage can be reduced by 0.4 V due to the formation of Er oxide. Moreover, it is observed that the equivalent oxide thickness is thinned down by 0.5 nm because the thickness of interfacial layer is significantly reduced, which is thought to be attributed to the strong binding capability of the implanted Er atoms with oxygen atoms. In addition, cross-sectional transmission electron microscopy experiment shows that the HfO2 layer with Er ion implantation is still amorphous after annealing at a high temperature. This Er ion implantation technique has the potential to be implemented as a band edge metal gate solution for NMOS without a capping layer, and may also satisfy the demand of the EOT reduction in 32 nm technology node.
