适用于SiC MOSFET的漏源电压积分自适应快速短路保护电路研究

SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。

SiC MOSFET高温栅氧可靠性研究

碳化硅SiC(silicon carbide)具有优良的电学和热学特性,是一种前景广阔的宽禁带半导体材料。SiC材料制成的功率MOSFET(metal-oxide-semiconductor field-effect transistor)非常适合应用于大功率领域,而高温栅氧可靠性是大功率MOSFET最需要关注的特性之一。通过正压高温栅偏试验和负压高温栅偏试验对比了自研SiC MOSFET和国外同规格SiC MOSFET的高温栅氧可靠性。负压高温栅偏试验结果显示自研SiC MOSFET与国外SiC MOSFET的阈值电压偏移量基本相等,阈值电压偏移量百分比最大相差在4.52%左右。正压高温栅偏试验的结果显示自研SiC MOSFET的阈值电压偏移量较小,与国外SiC MOSFET相比,自研SiC MOSFET的阈值电压偏移量百分比最大相差11%。自研器件占优势的原因是在SiC/SiO2界面处引入了适量的氮元素,钝化界面缺陷的同时,减少了快界面态的产生,使总的界面态密度被降到最低。

SiC MOSFET驱动特性及器件国产化后的影响分析

碳化硅金属氧化物半导体场效应晶体管SiC MOSFET(silicon carbide metal-oxide-semiconductor field-effect transistor)作为一种新型、广泛应用的开关器件,在实际应用中具有更快的开关速度和更低的器件损耗,可以提高变换器的效率,体现更好的性能。针对SiC MOSFET驱动特性,分析寄生参数对其的影响;搭建双脉冲实验平台,分析栅源电压与SiC MOSFET导通时间的关系;针对现有国产SiC MOSFET存在的不足之处,基于搭建的实验平台及其他电源产品,对SiC MOSFET进行国产化器件替代后导通时间、驱动损耗及负压幅值变化的相关分析。

动态高温反偏应力下的SiC MOSFET测试平台及其退化机理研究

为研究SiC MOSFET在动态漏源应力下的退化机理,开发了一种具有dVds/dt可调功能、最高可达80 V/ns的动态反向偏置测试平台。针对商用SiC MOSFET进行动态高温反偏实验,讨论高电压变化率的动态漏源应力对SiC MOSFET电学特性的影响。实验结果显示,器件的阈值电压和体二极管正向导通电压增加,说明器件JFET区上方的栅氧层和体二极管可能发生了退化。通过Sentaurus TCAD分析了在高漏源电压及高电压变化率下平面栅型SiC MOSFET的薄弱位置,在栅氧层交界处和体二极管区域设置了空穴陷阱,模拟动态高温反偏对SiC MOSFET动静态参数的影响。

Fabrication and Characterization of 1700 V 4H-SiC Vertical Double-Implanted Metal-Oxide-Semiconductor Field-Effect Transistors

The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.

SiC MOSFET的质子单粒子效应

SiC金属氧化物半导体场效应晶体管(MOSFET)在深空探测领域具有广阔的应用前景,但空间质子引发的单粒子效应(SEE)对航天器稳定运行造成了严重威胁。对平面栅结构与非对称沟槽栅结构的SiC MOSFET进行了能量为70、100与200 MeV的质子辐照实验。实验结果表明,两种SiC MOSFET的单粒子烧毁(SEB)阈值电压均大于额定漏源电压的75%;SEB阈值电压随质子能量升高而降低。对两种器件进行辐照后栅应力测试发现,两种结构的器件由于沟道不同而对栅应力的响应存在差异;不同的质子能量会在栅极引入不同程度的辐射损伤,低能质子更容易在栅氧化层发生碰撞而引入氧化物潜在损伤。该研究可为揭示SiC MOSFET质子SEE机理和评估抗辐射能力提供参考。

栅氧老化下SiC MOSFET开通瞬态栅极振荡特性研究

栅氧老化问题已成为制约碳化硅(SiC)金属半导体氧化物场效应管(metal oxide semiconductor field effect transistor,MOSFET)可靠性的关键因素,该文尝试利用SiC MOSFET高速开关在变换器中引起的高频开关振荡获取栅氧状态信息,重点研究栅氧老化对开通瞬态栅极高频振荡特性的影响。首先,分析SiC MOSFET栅氧老化机理及其对器件开通时间的影响。然后,建立开通瞬态栅极回路分阶段高频等效电路模型,揭示SiC MOSFET栅极开通振荡电流的形成机理和影响因素。最后,通过33 V高压栅偏加速老化实验进行验证。研究结果表明,随着栅氧老化程度的加深,SiC MOSFET阈值电压会逐渐增加而开通速度变慢,导致栅极开通振荡电流显著减小(约28%)。该文的工作有望为SiC MOSFET栅氧老化在线监测提供一种新的思路。

基于有源箝位技术的SiC MOSFET串联均压有源驱动电路研究

功率器件串联技术是实现高压应用的有效途径之一,而串联应用的主要制约因素是串联器件之间的动态均压问题。该文针对不均压条件下串联器件的关断行为进行了理论分析,探究不均压的产生机理,提出一种基于有源箝位技术的碳化硅金属-氧化物半导体场效应晶体管串联均压有源驱动,其利用有源箝位电路检测串联器件之间的电压不均衡,并箝位电压尖峰,通过反馈控制器件栅极电荷及开关瞬态行为实现均压。该方案不存在不均压的调节周期,即使在交变负载下依然能在每一个开关周期的关断时间内实现均压控制。此外,该文还详细介绍所提出方案的电路原理和参数设计过程,并通过试验验证该方案均压控制效果的有效性。结果表明,所提出方案具有有源箝位电路拓展性强的特点;是独立于原有栅极驱动电路的辅助电路,适用性强;且控制电路结构简单,无需可编程逻辑芯片和额外的信号隔离。

国产6.5 kV/400 A SiC MOSFET模块研制及电气特性研究

为满足当前新型电力系统中电能变换装备对器件高压、大容量、工作频率高、开关损耗低的需求,文中自主研制一款国内最高功率等级的6.5 kV/400 A碳化硅金属-氧化物-半导体场效应晶体管(metal-oxide-semiconductor field effect transistor,MOSFET)模块,并对其电气特性开展研究。首先,对模块的电路与封装结构进行设计,通过热仿真和阻抗测量手段,对所研制模块的热特性以及回路寄生参数进行分析;其次,对所研制的模块开展常温(25℃)及高温(150℃)下的静态、动态特性测量。测量结果表明,在常温、高温条件下,模块的阻断漏电流与栅源极漏电流微小,且开关损耗维持一致,具备较好的耐高温特性。同时,相较于同电压电流规格的硅绝缘栅双极型晶体管器件,模块开关损耗可降低72%以上。最后,搭建碳化硅器件连续运行工况实验平台,模拟器件在换流装备中的实际运行工况,对模块进行半桥正弦脉宽调制逆变连续运行实验。连续运行实验结果表明,该模块在电压3600 V、器件电流峰值280 A条件下连续运行1h无异常,初步验证模块具备工程应用能力。研究可为高压碳化硅MOSFET的研制及工程应用提供一定支撑。

基于栅极参考电压的SiC MOSFET栅极氧化物健康状态在线监测方法

栅极氧化物退化是限制SiC MOSFET进一步广泛应用的关键可靠性问题。在线监测能够实时获取栅极氧化物健康状态,是提升SiC MOSFET可靠性的重要手段,因此提出一种基于栅极参考电压的SiC MOSFET栅极氧化物健康状态在线监测方法,并详细介绍了利用栅极参考电压监测栅极氧化物健康状态的基本原理;提出一种栅极参考电压在线提取电路,经脉冲测试验证可以实现在线提取,经老化试验验证可以有效监测栅极氧化物健康状态。所提电路可以集成在栅极驱动中,不会显著增加系统复杂程度。

基于米勒平台电压的SiC MOSFET结温监测及校正方法

基于导通米勒平台电压的碳化硅金属-氧化物-半导体场效应晶体管(SiC metal-oxide-semiconductor field effect transistor,SiC MOSFET)结温监测方法受到功率回路负载电流和驱动电路电阻等参数的影响,会造成很大的测量误差。文中以降压变化电路中的SiC MOSFET为研究对象,研究了负载电流和驱动电阻、电感对导通米勒平台电压的影响,并进行了多组校准试验,建立了新的结温监测方法。试验验证了文中提出的结温监测及校正方法的有效性,且最大误差小于6.9℃。文中提出的结温检测方法可在具有不同负载电流和驱动电阻的变换器中准确获取结温信息。

Low working loss Si/4H-SiC heterojunction MOSFET with analysis of the gate-controlled tunneling effect

A silicon (Si)/silicon carbide (4H-SiC) heterojunction double-trench metal-oxide-semiconductor field effect transistor (MOSFET) (HDT-MOS) with the gate-controlled tunneling effect is proposed for the first time based on simulations. In this structure, the channel regions are made of Si to take advantage of its high channel mobility and carrier density. The voltage-withstanding region is made of 4H-SiC so that HDT-MOS has a high breakdown voltage (BV) similar to pure 4H-SiC double-trench MOSFETs (DT-MOSs). The gate-controlled tunneling effect indicates that the gate voltage (V_(G)) has a remarkable influence on the tunneling current of the heterojunction. The accumulation layer formed with positive VG can reduce the width of the Si/SiC heterointerface barrier, similar to the heavily doped region in an Ohmic contact. This narrower barrier is easier for electrons to tunnel through, resulting in a lower heterointerface resistance. Thus, with similar BV (approximately 1770 V), the specific on-state resistance (R_(ON-SP)) of HDT-MOS is reduced by 0.77 mΩ·cm^(2) compared with that of DT-MOS. The gate-to-drain charge (Q_(GD)) and switching loss of HDT-MOS are 52.14% and 22.59% lower than those of DT-MOS, respectively, due to the lower gate platform voltage (V_(GP)) and the corresponding smaller variation (ΔV_(GP)). The figure of merit (Q_(GD)×R_(ON-SP)) of HDT-MOS decreases by 61.25%. Moreover, the heterointerface charges can reduce RON-SP of HDT-MOS due to trap-assisted tunneling while the heterointerface traps show the opposite effect. Therefore, the HDT-MOS structure can significantly reduce the working loss of SiC MOSFET, leading to a lower temperature rise when the devices are applied in the system.

Modeling electric field of power metal-oxide-semiconductor field-effect transistor with dielectric trench based on Schwarz–Christoffel transformation

A power metal-oxide-semiconductor field-effect transistor(MOSFET) with dielectric trench is investigated to enhance the reversed blocking capability. The dielectric trench with a low permittivity to reduce the electric field at reversed blocking state has been studied. To analyze the electric field, the drift region is segmented into four regions, where the conformal mapping method based on Schwarz–Christoffel transformation has been applied. According to the analysis, the improvement in the electric field for using the low permittivity trench is mainly due to the two electric field peaks generated in the drift region around this dielectric trench. The analytical results of the electric field and the potential models are in good agreement with the simulation results.

Experimental I-V and C-V Analysis of Schottky-Barrier Metal-Oxide-Semiconductor Field Effect Transistors with Epitaxial NiSi2 Contacts and Dopant Segregation

We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H-SiC metal-oxide-semiconductor field-effect transistors （MOSF- FETs） have been fabricated and characterized. A sandwich- （nitridation-oxidation-nitridation） type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H-SiC/SiO2 were examined by the measurement of HF l-V, G-V, and C-V over a range of frequencies. The ideal C-V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H-SiC was reduced to 2 x 1011 eV-l.cm-2, the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak field- effect mobility is about 32.5 cm2.V-1 .s-1, and the maximum peak field-effect mobility of 38 cm2-V-1 .s-1 was achieved in fabricated lateral 4H-SiC MOSFFETs.

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors （MESFETs） with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.

SiC MOSFET新型负压关断串扰抑制驱动电路

基于碳化硅(SiC)材料的第三代宽禁带功率器件的出现,推动着电力电子变换器朝着高频化、高功率密度、小型化方向发展。但随着开关速度的提高,电路中寄生参数的影响越来越大,导致桥式变换器存在严重的串扰问题。文中根据SiC金属–氧化物半导体场效应晶体管(metal-oxidesemiconductor field-effect transistor,MOSFET)的工作特性,在RCD(电阻-电容-二极管)电平移位的驱动电路基础上提出一种新型的串扰抑制驱动电路。该电路通过电容和可控低压器件串联,并利用电路自身电压差驱动可控器件,为串扰电流提供一条低阻抗吸收回路,可有效地对串扰问题进行抑制。建立串扰抑制驱动电路的等效电路模型,推导得到该电路结构中电容容值与串扰电压峰值的量化关系,为该电路结构的设计提供理论依据。最后,通过双脉冲实验测试验证所提出电路的有效性及等效模型和理论计算的正确性。实验结果表明,与传统驱动电路相比,提出的串扰抑制驱动电路能够在不同电压与电流工况下,在保证开关速度的前提下,很大程度上抑制串扰尖峰电压。

用于SiC MOSFET开关电压测量的非接触式电场耦合电压传感器

准确测量碳化硅(silicon carbide,SiC)金属–氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)开关电压是评估SiC MOSFET开关特性、计算开关损耗、优化变换器设计的关键。随着SiC MOSFET开关速度、耐压及功率密度的提升,开关电压测量难的问题逐渐凸显,因此对电压传感器的带宽、耐压和侵入性提出了新的要求。该文以SiC MOSFET的开关电压为研究对象,根据目前开关电压的测量需求,提出一种利用电场耦合原理测量开关电压的非接触式电压传感器,并设计混合积分电路对传感器输出信号进行电压重构。在此基础上,通过仿真和计算着重分析电场耦合电压传感器的结构和电路参数的设计依据。传感器带宽范围为5Hz~260MHz,量程为-1000~+1000V,输入电容约为0.73pF,最后利用双脉冲测试,将其与商用示波器探头的测量结果进行对比,验证电场耦合电压传感器的准确性。

基于PZT压电陶瓷的SiC MOSFET缓冲吸收电路

在高速关断过程中,碳化硅(silicon carbide,SiC)金属-氧化物半导体场效应晶体管器件呈现出严重的电压过冲和振荡,降低器件电压裕量。通常,采用缓冲吸收电路改善SiC器件的关断电压轨迹。然而,现有研究忽略SiC器件与吸收电路的交互规律和工作温度对吸收电路性能的影响,限制缓冲吸收电路的应用。针对这些问题,该文提出一种基于锆钛酸铅(lead zirconate titanate,PZT)压电陶瓷的缓冲吸收电路,分析PZT的温度特性,通过建立半桥电路与PZT缓冲吸收电路的高精度交互模型,揭示PZT缓冲吸收电路与SiC器件的耦合规律,利用特征方程-根轨迹方法,定量刻画PZT缓冲吸收电路的参数设计域。对比评估工作温度对多种缓冲吸收电路性能的影响。实验结果表明,所提设计方法能很好地抑制关断电压过冲与振荡,验证设计方法的有效性。相较于传统RC缓冲吸收电路,PZT缓冲吸收电路在工作温度发生变动后,仍然具有很好的抑制效果,且抑制效果随工作温度的上升而不断增强。为SiC功率器件的暂态稳定性分析,以及功率模块和缓冲吸收电路的集成设计,提供有益的参考。

桥式电路中SiC MOSFET串扰峰值预测算法研究

文中针对串扰电压峰值与驱动回路阻抗间的非线性关系,分段分析共源电感存在时串扰产生机理,提出一种碳化硅(silicon carbide,SiC)金属氧化物半导体场效应管(metal-oxide-semiconductor field-effect transistor,MOSFET)串扰电压的分析模型及预测算法。所提算法综合考虑共源电感、非线性极间电容等寄生参数与探头接线的影响,可实现引脚测量串扰电压的准确计算及器件内部串扰电压的提取。进一步,该算法针对栅极回路建模,并利用实测数据引入漏源电压与源极电流时变性,可适用于多桥臂电路及不同器件工况。最后,实验结果表明,所提算法可精准预测不同关断态驱动阻抗下的串扰峰值,其正向峰值平均预测误差仅为3.2%。该算法可为SiC MOSFET驱动电路设计提供定量计算参考。