The design of adaptive sigma-delta A/D converter

The signal to noise ratio （SNR） of conventional sigma delta analog to digital converter （∑△ADC） reduces with input signal strength. The existing concept of adaptive quantization is applied to the design of ∑△ADC to improve SNR with high dynamic range. An adaptive algorithm and its circuit implementation is proposed. Because of the error due to the circuit implementation, an error self-calibration circuit is also designed. Simulation results indicate that SNR can he nearly independent of the signal strength.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.

A 16 bit Stereo Audio ΣΔ A/D Converter

A 16 bit stereo audio novel stability fifth-order ∑△ A/D converter that consists of switched capacitor ∑△ modulators, a decimation filter, and a bandgap circuit is proposed. A method for the stabilization of a high order single stage ∑△ modulator is also proposed. A new multistage comb filter is used for the front end decimation filter. The ∑△ A/D converter achieves a peak SNR of 96dB and a dynamic range of 96dB. The ADC was implemented in 0. 5μm 5V CMOS technology. The chip die area occupies only 4. 1mm × 2.4mm and dissipates 90mW.

基于D-分割法的直流变换器遗传自抗扰控制器设计

针对光伏发电系统中DC-DC变换器由于负载和工作环境条件变化等扰动引起的输出波动问题,提出一种基于D-分割法的直流变换器遗传自抗扰控制器(ADRC)设计方法。该方法适用于设计光伏发电领域中的双向DC-DC变换器,采用D-分割法获得满足闭环系统鲁棒稳定的ADRC控制器参数范围;利用具有全局寻优能力的遗传算法,按综合性能指标在该范围内进行参数寻优。实验结果表明,所提基于D-分割法的直流变换器遗传自抗扰控制器设计方法能有效抑制微网母线侧的电压波动和负载突变,提高控制器的鲁棒性,增强光伏发电系统的动态响应性能和抗干扰能力。

一种高速A/D转换器时域重构技术研究

A/D转换器在航空航天系统中的重要元器件,随着器件转换时钟频率不断提高而其工作环境不断恶化,如何准确测试其时间参数对于全面评价A/D转换器性能特别重要。目前对于高速A/D转换器时间参数测试,主流方法是通过示波器直接测试其输出,该方法对于示波器采样速度要求比较高。文章提出一种高速A/D转换器时域重构技术,可以通过计算机数字信号处理方法来实现高速A/D转换器时间参数测试,同时避免对示波器采样速度的依赖。同时,在研究高速A/D转换器时域重构技术方法及其应用的基础上,通过了相关试验验证。

Numeric Simulation of Single Passage Ternary Turbulence Model in Hydraulic Torque Converter

Based on the renormalization group theory, a hydraulic torque converter 3 D turbulent single flow passage model is constructed and boundary condition is determined for analyzing the influence of the fluid field characteristic and parameters on the macroscopic model. Numerical simulation of the single fluid path is processed by computational fluid dynamics and the calculated results approach to experimental data well, and especially in low transmission ratio the torque and head results are more close to experimental data than the calculated results of beam theory. This shows that the appropriate ternary analysis method and reasonable assumption of boundary condition may analyze the flow field more precisely and predict the performance of torque converter more accurately.

A 10bit 2GHz CMOS D/A Converter for High-Speed System Applications

This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.

Performance Optimization of Torque Converters Based on Modified 1D Flow Model

A methodology for performance optimization of torque converters is put forward based on the one-dimensional (1D) flow model. It is found that the inaccuracy of 1D flow model for predicting hydraulic performance at the low speed ratio is mainly caused by the separation phenomenon at the stator cascade which is induced by large flow impinging at the pressure side of the stator blades. A semi-empirical separation model is presented and incorporated to the original 1D flow model. It is illustrated that the improved model is able to predict the circumferential velocity components accurately, which can be applied to performance optimization. Then, the Pareto front is obtained by using the genetic algorithm (GA) in order to inspect the coupled relationship among stalling impeller torque capacity, stalling torque ratio and efficiency. The efficiency is maximized on the premise that a target stalling impeller torque capacity and torque ratio are achieved. Finally, the optimized result is verified by the computational fluid dynamics(CFD) simulation, which indicates that the maximal efficiency is increased by 0.96%.

Numerical simulation of the flow field of a flat torque converter

A flexible flat torque converter was proposed to fulfill the requirement of miniaturization and power density maximization for automobiles.Constructed by two arcs joined by lines,the torus was designed directly from design path.The influence of flatness on the performance of the torque converter was evaluated.The software CFX and standard k-ε model were adopted to simulate the internal flow fields of the torque converter under different flatness ratios.The results indicated that the performance of the torque converter got worse as the flatness declined,but the capacity of pump increased.The efficiency and the torque ratio dropped slightly as the flatness ratio decreased.So the torque converter could be squashed appropriately to get high power density without too much efficiency sacrifice.But when the flatness ratio was below 0.2,there was a significant drop in the efficiency.

一种14位80 MS/s流水线型A/D转换器设计

基于SMIC 0.18μm CMOS工艺,设计了一种14位80 MS/s的流水线型A/D转换器(ADC)。为了降低ADC整体功耗,首级电路采用2.5 bit无采样保持(SHA-less)结构。进一步,基于套筒式共源-共栅结构提出了一种改进型运放,通过复制尾电流反馈技术和增益提高技术的应用提升了运放的速度和增益,且功耗较低。比较器仅采用动态锁存器以减小级间延迟。还采用了栅压自举开关降低开关导通电阻,提高采样网络带宽和线性度。芯片测试结果表明,在1.8 V电源电压、采样频率为80 MHz的条件下,输入信号频率分别为10 MHz和70 MHz时,ADC的动态参数性能相差不大。其中,输入信号频率为70 MHz时,信噪失真比(SNDR)为72.2 dB,无杂散动态范围(SFDR)为85.82 dB,有效位数(ENOB)为11.7 bit,品质因数(FoM)为0.38 pJ/(conv·step)。

血清GSDMD、ACE2在小儿川崎病中的表达水平及临床意义研究

目的 探索血清焦孔素蛋白D(GSDMD)、血管紧张素转化酶2(ACE2)在小儿川崎病(KD)患儿中的表达水平及临床意义。方法 收集2020年1月至2022年1月该院诊治的90例KD患儿为KD组,根据KD患儿是否发生冠状动脉损伤(CAL),将KD组分为CAL组(32例)和非CAL组(58例),选取同期因急性呼吸道感染发热住该院的患儿50例为发热对照组,另选取同期该院儿外科行择期手术的腹股沟斜疝患儿50例为对照组。采用酶联免疫吸附试验检测血清GSDMD、ACE2水平。Pearson相关分析血清GSDMD、ACE2与临床指标的相关性。多因素Logisitic回归分析KD患者发生CAL的影响因素。受试者工作特征(ROC)曲线分析血清GSDMD、ACE2对KD患儿发生CAL的诊断价值。结果 KD组血清GSDMD、ACE2水平高于发热对照组和对照组,差异有统计学意义(均P<0.05)。相比于非CAL组,CAL组KD患儿发热持续时间、丙种球蛋白治疗时间、红细胞沉降率、血小板计数、C反应蛋白、GSDMD、ACE2水平均明显较高,而血钠、白蛋白明显较低,差异有统计学意义(均P<0.05)。Pearson相关分析结果,KD组患儿血清GSDMD、ACE2水平与发热持续时间、丙种球蛋白治疗时间、红细胞沉降率、血小板计数、C反应蛋白呈正相关(均P<0.05),与血钠、白蛋白呈负相关(均P<0.05)。多因素Logistic回归分析结果显示,血清GSDMD、ACE2升高是影响KD患儿发生CAL的独立危险因素。ROC曲线分析结果显示,血清GSDMD、ACE2两项联合检测KD患儿发生CAL的曲线下面积(AUC)及其95%CI为0.918(0.868~0.949),明显大于血清GSDMD、ACE2单项检测的AUC及其95%CI[依次为0.838(0.789~0.887)、0.865(0.811~0.912)],差异有统计学意义(Z=5.116、4.217,均P<0.05)。结论 血清GSDMD、ACE2两项联合检测对于KD患儿发生CAL具有较高的诊断价值。

A 128×128 SPAD LiDAR sensor with column-parallel 25 ps resolution TA-ADCs

This paper presents a design of single photon avalanche diode(SPAD)light detection and ranging(LiDAR)sensor with 128×128 pixels and 128 column-parallel time-to-analog-merged-analog-to-digital converts(TA-ADCs).Unlike the conventional TAC-based SPAD LiDAR sensor,in which the TAC and ADC are separately implemented,we propose to merge the TAC and ADC by sharing their capacitors,thus avoiding the analog readout noise of TAC’s output buffer,improving the conversion rate,and reducing chip area.The reverse start-stop logic is employed to reduce the power of the TA-ADC.Fabricated in a 180 nm CMOS process,our prototype sensor exhibits a timing resolution of 25 ps,a DNL of+0.30/−0.77 LSB,an INL of+1.41/−2.20 LSB,and a total power consumption of 190 mW.A flash LiDAR system based on this sensor demonstrates the function of 2D/3D imaging with 128×128 resolution,25 kHz inter-frame rate,and sub-centimeter ranging precision.

Analytical Modelling and Experiment of Novel Rotary Electro-Mechanical Converter with Negative Feedback Mechanism for 2D Valve

The manufacturing of spiral groove structure of two-dimensional valve(2D valve)feedback mechanism has shortcomings of both high cost and time-consuming.This paper presents a novel configuration of rotary electro-mechanical converter with negative feedback mechanism(REMC-NFM)in order to replace the feedback mechanism of spiral groove and thus reduce cost of valve manufacturing.In order to rapidly and quantitative evaluate the driving and feedback performance of the REMC-NFM,an analytical model taking leakage flux,edge effect and permeability nonlinearity into account is formulated based on the equivalent magnetic circuit approach.Then the model is properly simplified in order to obtain the optimal pitch angle.FEM simulation is used to study the influence of crucial parameters on the performance of REMC-NFM.A prototype of REMC-NFM is designed and machined,and an exclusive experimental platform is built.The torque-angle characteristics,torque-displacement characteristics,and magnetic flux density in the working air gap with different excitation currents are measured.The experimental results are in good agreement with the analytical and FEM simulated results,which verifies the correctness of the analytical model.For torque-angle characteristics,the overall torque increases with both current and rotation angle,which reaches about 0.48 N·m with 1.5 A and 1.5°.While for torque-displacement characteristics,the overall torque increases with current yet decrease with armature displacement due to the negative feedback mechanism,which is about 0.16 N·m with 1.5 A and 0.8 mm.Besides,experimental results of conventional torque motor are compared with counterparts of REMC-NFM in order to validate the simplified model.The research indicates that the REMC-NFM can be potentially used as the electro-mechanical converter for 2D valves in civil servo areas.

The Design of A/D Converter Circuit Adopting the Technology of PWM

This text has expounded the working principle of realizing A/D conversion that utilizes the timer within MCU and combinesthe technology of PWM. The design of hardware circuit, improved gradual approached trial arithmetic and relevant program design arediscussed in detail. And it has analyzed the resolution of A/D converter based on the technology of PWM, etc.

基于层次分析法与改进D-S理论的阀水冷系统状态评估

为了及时评估保障换流阀可靠运行的阀水冷系统运行状态,首先,分析了换流站阀水冷系统整体构成,选取主要历史数据和实时数据构建了评估指标体系,通过三角形函数和半梯形函数以及专家调查法确定各个指标的隶属度;其次,基于层次分析法确定各个评估指标权重,改进D-S理论建立阀水冷系统运行状态评估模型;最后,通过采集实际工程阀水冷系统主要指标数据对模型进行了验证,并以阀水冷系统滤芯清洗前后数据为例对评估结果进行了对比。结果表明,所建模型能够对阀水冷系统运行状态做出准确识别和评估,有利于运维人员及时掌控阀水冷系统运行状态,保障其可靠运行。

自适应Sigma-Delta A/D转换器的设计

对于传统的Sigma DeltaA/D转换器 (ADC) ,其信噪比 (SNR)将随着输入信号强度的减小而降低 .因此 ,本文根据自适应理论提出一种自适应ADC的解决方案及相应的电路实现 .在充分考虑了在电路实现中误差的存在 ,给出了误差自校正电路 .仿真结果表明 ,这种自适应ADC的SNR几乎与输入信号的强度无关 .

Sigma-Delta调制器非理想特性建模

文章对三阶单环路结构的高阶sigma-deltaA/D调制器的非理想特性,包括时钟抖动、MOS开关噪声、比较器迟滞性、放大器的输入噪声、单位增益带宽和有限直流增益等,进行了分析,提出了基于Matlab的高层次建模方法。通过系统仿真确定关键的电路参数和性能指标,在较高层次指导A/D转换器的电路结构级和晶体管级设计。

一种高速连续时间Sigma-Delta ADC设计

在TSMC 0.18μm CMOS工艺下设计了一款宽带宽、低功耗的连续时间Sigma-Delta ADC调制器。该调制器可以应用于无线通信、视频、医疗和工业成像等领域,它采用三阶RC积分环路滤波结构,提高了可达到的精度。针对环路延时降低系统稳定性的问题,在环路中引入半个采样周期的延时,以此提高调制器的精度;同时采用非回零的DAC结构来减小系统对时钟抖动的敏感度。通过结构的选取和非回零的DAC结构的使用,调制器对时钟抖动有很强的忍受能力。该Sigma-Delta ADC的带宽可以达到5 MHz,信噪比可达63.6 dB(10位),整个调制器在1.8 V的电压下,功耗仅为32 mW。

高精度高摆幅多工位ADC测试系统设计

基于V93000 ATE设计了一种采用外加电源升压变换模块及可变增益仪器仪表运算放大器,以解决大输入摆幅高精度多工位ADC的量产测试需求的测试方案。理论分析和测试验证结果表明,该ADC测试系统可分别产生峰峰值超过29 V的Ramp波和正弦波测试信号,测试信号SNR优于105 dB、THD优于-103 dB,可以满足16 bit、±10 V甚至以上高输入摆幅多工位ADC的大批量量产测试需求。

A 78-MHz BW Continuous-Time Sigma-Delta ADC with Programmable VCO Quantizer

This article presents a high speed third-order continuous-time(CT)sigma-delta analog-to-digital converter(SDADC)based on voltagecontrolled oscillator(VCO),featuring a digital programmable quantizer structure.To improve the overall performance,not only oversampling technique but also noise-shaping enhancing technique is used to suppress in-band noise.Due to the intrinsic first-order noise-shaping of the VCO quantizer,the proposed third-order SDADC can realize forth-order noise-shaping ideally.As a bright advantage,the proposed programmable VCO quantizer is digital-friendly,which can simplify the design process and improve antiinterference capability of the circuit.A 4-bit programmable VCO quantizer clocked at 2.5 GHz,which is proposed in a 40 nm complementary metaloxide semiconductor(CMOS)technology,consists of an analog VCO circuit and a digital programmable quantizer,achieving 50.7 dB signal-to-noise ratio(SNR)and 26.9 dB signal-to-noise-and-distortion ration(SNDR)for a 19 MHz−3.5 dBFS input signal in 78 MHz bandwidth(BW).The digital quantizer,which is programmed in the Verilog hardware description language(HDL),consists of two-stage D-flip-flop(DFF)based registers,XOR gates and an adder.The presented SDADC adopts the cascade of integrators with feed-forward summation(CIFF)structure with a third-order loop filter,operating at 2.5 GHz and showing behavioral simulation performance of 92.9 dB SNR over 78 MHz bandwidth.