Coordinated Capacitor Voltage Balancing Method for Cascaded H-bridge Inverter with Supercapacitor and DC-DC Stage

Cascaded H-bridge inverter(CHBI) with supercapacitors(SCs) and dc-dc stage shows significant promise for medium to high voltage energy storage applications. This paper investigates the voltage balance of capacitors within the CHBI, including both the dc-link capacitors and SCs. Balance control over the dc-link capacitor voltages is realized by the dcdc stage in each submodule(SM), while a hybrid modulation strategy(HMS) is implemented in the H-bridge to balance the SC voltages among the SMs. Meanwhile, the dc-link voltage fluctuations are analyzed under the HMS. A virtual voltage variable is introduced to coordinate the balancing of dc-link capacitor voltages and SC voltages. Compared to the balancing method that solely considers the SC voltages, the presented method reduces the dc-link voltage fluctuations without affecting the voltage balance of SCs. Finally, both simulation and experimental results verify the effectiveness of the presented method.

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.

Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

A Novel Full Differential Feedforward Fourth-Order Bandpass Sigma-Delta Modulator

In this paper,in order to reduce power consumption and chip area,as well as to improve the performance of the bandpass sigma-delta modulator,a novel full differential feedforward fourth-order bandpass sigma-delta modulator was proposed. It used a resonator based on Salo architecture,which employed doublesampling and double-delay technique. The results show that the proposed modulator can achieve lower power consumption and a lower capacitive load than the conventional bandpass modulators on the platform of Simulink. The circuit is implemented with TSMC0. 18 μm CMOS process and operates at a sampling frequency of 20 MHz, 80 MHz effective sampling frequency. Furthermore,it consumes 21. 2 mW from a 1. 8 V supply. The simulated peak signal-to-noise ratio( SNR) is 85. 9 dB and the dynamic range( DR) is 91 dB with 200 kHz bandwidth.

Synchronization analysis on cascaded multilevel converters with distributed control

Cascaded multilevel converters built with integrated modules have many advantages such as increased power density,flexible distributed control,multi-functionality,increased reliability and short design cycles.However,the system performance will be affected due to the synchronization errors among each integrated modules.This paper analyzes the impact of the three kinds of synchronization errors on the whole system performance,as well as detailed synchronization implementation.Some valuable conclusions are derived from the theoretical analysis,simulations and experimental results.

THD Analysis of Cascaded H-Bridge Inverter with Fuzzy Logic Controller

In recent days, the multilevel inverter technology is widely applied to domestic and industrial applications for medium voltage conversion. But, the power quality issues of the multilevel inverter limit the usage of much sensitive equipment like medical instruments. The lower distortion level of the output voltage and current can generate a quality sinusoidal output voltage in inverters and they can be used for many applications. The harmonics can cause major problems in equipments due to the nonlinear loads connected with the power system. So, it is necessary to minimize the losses to raise its overall efficiency. In this paper, a new topology of seven level asymmetrical cascaded H-bridge multilevel inverter with a Fuzzy logic controller had been implemented to reduce the Total Harmonic Distortion (THD) and to improve the overall performance of the inverter. The proposed model is well suited for use with a solar PV application. In this topology, only six IGBT switches are used with three different voltage ratings of PV modules (1:2:4). The lower number of semiconductor switches leads to minimizing overall di/dt ratings and voltage stress on each switches and switching losses. The gate pulses generated by Sinusoidal Pulse Width Modulation (SPWM) technique with a Fuzzy logic controller are also introduced. A buck-boost converter is used to maintain the constant PV voltage level integrated by an MPPT technique followed by Perturb and Observer algorithm is also implemented. The MPPT is used to harness the maximum power of solar radiations under its various climatic conditions. The new topology is evaluated by a Matlab/Simulink model and compared with a hardware model. The results proved that the THD achieved by this topology is 1.66% and realized that it meets the IEEE harmonic standards.

OFDM with Generalized Cascade Index Modulation for Secure Communications

Cascade index modulation(CIM) is a recently proposed improvement of orthogonal frequency division multiplexing with index modulation(OFDM-IM) and achieves better error performance.In CIM, at least two different IM operations construct a super IM operation or achieve new functionality. First, we propose a OFDM with generalized CIM(OFDM-GCIM) scheme to achieve a joint IM of subcarrier selection and multiple-mode(MM)permutations by using a multilevel digital algorithm.Then, two schemes, called double CIM(D-CIM) and multiple-layer CIM(M-CIM), are proposed for secure communication, which combine new IM operation for disrupting the original order of bits and symbols with conventional OFDM-IM, to protect the legitimate users from eavesdropping in the wireless communications. A subcarrier-wise maximum likelihood(ML) detector and a low complexity log-likelihood ratio(LLR) detector are proposed for the legitimate users. A tight upper bound on the bit error rate(BER) of the proposed OFDM-GCIM, D-CIM and MCIM at the legitimate users are derived in closed form by employing the ML criteria detection. Computer simulations and numerical results show that the proposed OFDM-GCIM achieves superior error performance than OFDM-IM, and the error performance at the eavesdroppers demonstrates the security of D-CIM and M-CIM.

A 3V 5.88mW 13b 400kHz Sigma-Delta Modulator with 84dB Dynamic Range

This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.

High-Consistency Behavior Modeling of a Switched-Capacitor Sigma-Delta Modulator in SIMULINK

To improve the simulation accuracy of SIMULINK, a novel inclusive behavior model of an integrator is proposed that introduces the effects of different circuit nonidealities of a switched-capacitor sigma-delta modulator into SIMULIK simulation. The nonlinear DC gain and nonlinear settling process are introduced into the op-amp module. The signaldependent charge injection and nonlinear resistance are introduced into the switch module. In addition, the noise source including flicker and thermal noise is introduced into system as an independent module. The novel model is verified by SIMULINK behavioral simulations. The results are compared with results from circuit level simulation in Cadence SPICE using TSMC 0.35μm mixed signal technology. It shows that the novel model succeeds in introducing the influences of the nonidealities into behavior simulation to more realistically describe the circuit performances and increase the accuracy of SIMULINK simulation.

Optical Nonlinearity in a Novel Optical Signal Regeneration System Based on Cross-Gain Modulation Using Cascaded Semiconductor Optical Amplifiers

We propose a novel optical signal regeneration system based on wavelength converters by use of cross gain modulation in cascaded semiconductor optical amplifiers. The nonlinearity in optical input/output characteristics and eye opening using NRZ signal were archived.

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpass ∑△ modulator is presented for digital intermediatefrequency （IF） receivers. The circuit operates at a sampling frequency of 100 MHz. The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators. The modulator is implemented in a 0.13-μm standard CMOS process. The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB, respectively, over a bandwidth of 200 kHz centered at 25 MHz, and the power dissipation is 8.2 mW at a 1.2 V supply.

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.

A 1-V 60-μW 85-dB dynamic range continuous-time third-order sigma-delta modulator

A 1-V third order one-bit continuous-time（CT） EA modulator is presented. Designed in the SMIC mixedsignal 0.13-μm CMOS process, the modulator utilizes active RC integrators to implement the loop filter. An efficient circuit design methodology for the CT ZA modulator is proposed and verified. Low power dissipation is achieved through the use of two-stage class A/AB amplifiers. The presented modulator achieves 81.4-dB SNDR and 85-dB dynamic range in a 20-kHz bandwidth with an over sampling ratio of 128. The total power consumption of the modulator is only 60 μW from a 1-V power supply and the prototype occupies an active area of 0.12 mm^2.

Hierarchical Digital Modulation Classification Using Cascaded Convolutional Neural Network

Automatic modulation classification(AMC)aims to identify the modulation format of the received signals corrupted by the noise,which plays a major role in radio monitoring.In this paper,we propose a novel cascaded convolutional neural network(CasCNN)-based hierarchical digital modulation classification scheme,where M-ary phase shift keying(PSK)and M-ary quadrature amplitude modulation(QAM)modulation formats are considered to be classified.In CasCNN,two-block convolutional neural networks are cascaded.The first block network is utilized to classify the different classes of modulation formats,namely PSK and QAM.The second block is designed to identify the indexes of the modulations in the same PSK or QAM class.Moreover,it is noted that the gird constellation diagram extracted from the received signal is utilized as the inputs to the CasCNN.Extensive simulations demonstrate that CasCNN yields performance gain and performs stronger robustness to frequency offset compared with other recent methods.Specifically,CasCNN achieves 90%classification accuracy at 4 dB signal-to-noise ratio when the symbol length is set as 256.

采用Mash2-1架构的高精度Sigma-Delta ADC设计

鉴于模数转换器(ADC)在芯片和混合信号处理领域举足轻重的作用,为探索进一步提高模数转换器精度的可能性,满足当今应用系统对模数转换精度的新需求,设计一款基于Mash2-1级联架构的sigma-delta ADC。设计采用TSMC 180 nm CMOS工艺,在完成调制器电路的同时,使用Verilog代码方式实现了配套的误差消除以及数字抽取滤波器。对调制器进行了建模及非理想因素的分析,并通过使用斩波调制技术等手段对电路的非理想性进行优化。经仿真验证,结果表明,本设计在3.3 V电源、27℃工作环境、TT典型工艺条件下,表现出优异的信噪比,总谐波失真等性能指标也较理想,适用于高精度、低失真的应用场合。

An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers

A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.

基于改进Cascade RCNN的输电线路防振锤脱落检测方法

无人机巡检输电线路时,因拍摄角度和距离问题,容易出现被输电线遮挡和远距离拍摄的防振锤脱落目标,导致目标特征被遮挡且分辨率较低,且部分防振锤出现滑移现象,导致目标识别准确率降低。针对以上问题,提出一种基于改进Cascade RCNN的防振锤脱落检测网络。第一,设计了对比学习网络,将正负样本与真实样本的特征进行对比学习,利用对比损失函数训练网络,使其能更加关注到被遮挡的防振锤脱落目标,提升其特征提取能力;第二,进行了分类器增强操作,筛选出网络级联结构中回归效果较好的感兴趣区域并送入最后的分类回归队列中,提高了分类器的分类能力,进而提升检测目标的分类分数;第三,设计了并行注意力机制模块,整合网络提取的特征,增大关键特征的权重,使网络关注到图像中更关键的区域;在特征金字塔中,将双线性插值方法代替为反卷积,提升特征还原能力。经交叉验证实验结果表明,改进后的模型召回率、精确率和平均精度达到了97.5%,91.0%和92.0%,相比基线模型分别提高了6.9%,28.4%和8.0%。

Soliton pulse compression through cascaded quadratic nonlinearity in difference-frequency generation

Cascaded nonlinearity based soliton pulse compression in the process of femtosecond difference frequency generation is studied theoretically. A set of simplified coupled wave equations under the conditions of large phase mismatch and matched group velocities is obtained,which reveals the physical mechanism of soliton compression in this process. Numerical simulations demonstrate that in the presence of group velocity dispersion and equivalent cross phase modulation,both the pump and the signal pulses can be compressed with a high compression ratio.

Tunable fiber laser based on a cascaded structure consisting of in-line MZI and traditional MZI

A tunable erbium-doped fiber（EDF） laser with a cascaded structure consisting of in-line Mach-Zehnder interferometer（MZI） and traditional MZI is proposed. The transmission spectrum of the in-line MZI is modulated by the traditional MZI, which determines the period of the cascaded structure, while the in-line MZI＇s transmission spectrum is the outer envelope curve of the cascaded structure＇s transmission spectrum. A stable single-wavelength lasing operation is obtained at 1 527.14 nm. The linewidth is less than 0.07 nm with a side-mode suppression ratio（SMSR） over 48 d B. Fixing the in-line MZI structure on a furnace, when the temperature changes from 30 ℃ to 230 ℃, the central wavelength can be tuned within the range of 12.4 nm.

单相级联型多电平变换器直流纹波电压分析及抑制策略

级联H桥型多电平变换器采用移相变压器+整流供电时具有功率因数高、输出电压谐波含量低等优点,在大功率工业领域范围内得到了广泛应用。传统的调制算法都以假设直流母线电压恒定为前提,然而在直流侧会出现低频纹波并被调制和传输到负载,导致输出电压波形畸变。目的为了探讨级联H桥单元供电侧存在大量直流纹波电压导致输出负载电压波形畸变的问题,方法本文首先采用双重傅里叶理论分析直流纹波电压,在此基础上引入一种直流纹波前馈补偿策略,通过测量每个级联H桥的直流侧实际输入电压除以电压基准值并与传统载波信号相乘,进而与调制电压进行载波移相调制;同时采用矢量控制,通过FFT变换虚拟出无功电压,以获得更快的收敛速度、更高的稳定性和更小的振荡。结果仿真和实验结果表明,所提调制算法和控制策略可有效抑制负载电压中的低次谐波,减小输出电压波形畸变,实现逆变电源的快速动态响应和无稳态误差控制。结论实验结果验证了本文所采用的调制策略和控制策略的可行性与合理性。