Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

The variations of single event transient(SET)pulse width of high-LET heavy ion irradiation in 16-nm-thick bulk silicon fin field-effect transistor(Fin FET)inverter chains with different driven strengths are measured at different temperatures.Three-dimensional(3D)technology computer-aided design simulations are carried out to study the SET pulse width and saturation current varying with temperature.Experimental and simulation results indicate that the increase in temperature will enhance the parasitic bipolar effect of bulk Fin FET technology,resulting in the increase of SET pulse width.On the other hand,the increase of inverter driven strength will change the layout topology,which has a complex influence on the SET temperature effects of Fin FET inverter chains.The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

Estimation of pulsed laser-induced single event transient in a partially depleted silicon-on-insulator 0.18-μm MOSFET

In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.

Temperature dependence of the P-hit single event transient pulse width in a three-transistor inverter chain

A comparison of the temperature dependence of the P-hit single event transient （SET） in a two-transistor （2T） inverter with that in a three-transistor （3T） inverter is carried out based on a three-dimensional numerical simulation. Due to the significantly distinct mechanisms of the single event change collection in the 2T and the 3T inverters, the temperature plays different roles in the SET production and propagation. The SET pulse will be significantly broadened in the 2T inverter chain while will be compressed in the 3T inverter chain as temperature increases. The investigation provides a new insight into the SET mitigation under the extreme environment, where both the high temperature and the single event effects should be considered. The 3T inverter layout structure （or similar layout structures） will be a better solution for spaceborne integrated circuit design for extreme environments.

Parasitic bipolar amplification in a single event transient and its temperature dependence

Using three-dimensional technology computer-aided design （TCAD） simulation, parasitic bipolar amplification in a single event transient （SET） current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both ]30-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.

Temperature and drain bias dependence of single event transient in 25-nm FinFET technology

In this paper, we investigate the temperature and drain bias dependency of single event transient （SET） in 25-nm fin field-effect-transistor （FinFET） technology in a temperature range of 0-135 ℃ and supply voltage range of 0.4 V- 1.6 V. Technology computer-aided design （TCAD） three-dimensional simulation results show that the drain current pulse duration increases from 0.6 ns to 3.4 ns when the temperature increases from 0 to 135 ℃. The charge collected increases from 45.5 ℃ to 436.9 fC and the voltage pulse width decreases from 0.54 ns to 0.18 ns when supply voltage increases from 0.4 V to 1.6 V. Furthermore, simulation results and the mechanism of temperature and bias dependency are discussed.

Laser-Induced Single Event Transients in Local Oxidation of Silicon and Deep Trench Isolation Silicon-Germanium Heterojunction Bipolar Transistors

We present a study on the single event transient （SET） induced by a pulsed laser in different silicon-germanium （SiGe） heterojunction bipolar transistors （HBTs） with the structure of local oxidation of silicon （LOCOS） and deep trench isolation （DTI）. The experimental results are discussed in detail and it is demonstrated that a SiGe HBT with the structure of LOCOS is more sensitive than the DTI SiGe HBT in the SET. Because of the limitation of the DTI structure, the charge collection of diffusion in the DTI SiGe HBT is less than that of the LOCOS SiGe HBT. The SET sensitive area of the LOCOS SiGe HBT is located in the eollector-substrate （C/S） junction, while the sensitive area of the DTI SiGe HBT is located near to the collector electrodes.

Angular dependence of proton-induced single event transient in silicon-germanium heterojunction bipolar transistors

We investigate the angular dependence of proton-induced single event transient(SET) in silicon-germanium heterojunction bipolar transistors. Experimental results show that the overall SET cross section is almost independent of proton incident angle. However, the proportion of SET events with long duration and high integral charge collection grows significantly with the increasing angle. Monte Carlo simulations demonstrate that the integral cross section of proton incident events with high ionizing energy deposition in the sensitive volume tends to be higher at larger incident angles, which is associated with the angular distribution of proton-induced secondary particles and the geometry of sensitive volume.

New insight into the parasitic bipolar amplification effect in single event transient production

In this paper, a new method is proposed to study the mechanism of charge collection in single event transient （SET） production in 90 nm bulk complementary metal oxide semiconductor （CMOS） technology. We find that different from the case in the pMOSFET, the parasitic bipolar amplification effect （bipolar effect） in the balanced inverter does not exist in the nMOSFET after the ion striking. The influence of the suhstrate process on the bipolar effect is also studied in the pMOSFET. We find that the bipolar effect can be effectively mitigated by a buried deep P＋-well layer and can be removed by a buried SO2 layer.

Experimental verification of the parasitic bipolar amplification effect in PMOS single event transients

The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.

Single-event-transient effect in nanotube tunnel field-effect transistor with bias-induced electron–hole bilayer

The single event transient(SET)effect in nanotube tunneling field-effect transistor with bias-induced electron–hole bilayer(EHBNT-TFET)is investigated by 3-D TCAD simulation for the first time.The effects of linear energy transfer(LET),characteristic radius,strike angle,electrode bias and hit location on SET response are evaluated in detail.The simulation results show that the peak value of transient drain current is up to 0.08 m A for heavy ion irradiation with characteristic radius of 50 nm and LET of 10 Me V·cm^(2)/mg,which is much higher than the on-state current of EHBNTTFET.The SET response of EHBNT-TFET presents an obvious dependence on LET,strike angle,drain bias and hit location.As LET increases from 2 Me V·cm^(2)/mg to 10 Me V·cm^(2)/mg,the peak drain current increases monotonically from 0.015 mA to 0.08 mA.The strike angle has an greater impact on peak drain current especially for the smaller characteristic radius.The peak drain current and collected charge increase by 0.014 mA and 0.06 fC,respectively,as the drain bias increases from 0.1 V to 0.9 V.Whether from the horizontal or the vertical direction,the most sensitive hit location is related to wt.The underlying physical mechanism is explored and discussed.

The modulation effect of substrate doping on multi-node charge collection and single-event transient propagation in 90-nm bulk complementary metal-oxide semiconductor technology

Variation of substrate background doping will affect the charge collection of active and passive MOSFETs in complementary metal-oxide semiconductor （CMOS） technologies, which are significant for charge sharing, thus affecting the propagated single event transient pulsewidths in circuits. The trends of charge collected by the drain of a positive channel metal-oxide semiconductor （PMOS） and an N metal-oxide semiconductor （NMOS） are opposite as the substrate doping increases. The PMOS source will inject carriers after strike and the amount of charge injected will irlcrease as the substrate doping increases, whereas the source of the NMOS will mainly collect carriers and the source of the NMOS can also inject electrons when the substrate doping is light enough. Additionally, it indicates that substrate doping mainly affects the bipolar amplification component of a single-event transient current, and has little effect on the drift and diffusion. The change in substrate doping has a much greater effect on PMOS than on NMOS.

Negative bias temperature instability induced single event transient pulse narrowing and broadening

The effect of negative bias temperature instability （NBTI） on a single event transient （SET） has been studied in a 130 nm bulk silicon CMOS process based on 3D TCAD device simulations. The investigation shows that NBTI can result in the pulse width and amplitude of SET narrowing when the heavy ion hits the PMOS in the high-input inverter; but NBTI can result in the pulse width and amplitude of SET broadening when the heavy ion hits the NMOS in the low-input inverter. Based on this study, for the first time we propose that the impact of NBTI on a SET produced by the heavy ion hitting the NMOS has already been a significant reliability issue and should be of wide concern, and the radiation hardened design must consider the impact of NBTI on a SET.

Line-edge roughness induced single event transient variation in SOI Fin FETs

The impact of process induced variation on the response of SOI Fin FET to heavy ion irradiation is studied through 3-D TCAD simulation for the first time. When Fin FET biased at OFF state configuration（Vgs D0, Vds DVdd/ is struck by a heavy ion, the drain collects ionizing charges under the electric field and a current pulse（single event transient, SET） is consequently formed. The results reveal that with the presence of line-edge roughness（LER）, which is one of the major variation sources in nano-scale Fin FETs, the device-to-device variation in terms of SET is observed. In this study, three types of LER are considered： type A has symmetric fin edges, type B has irrelevant fin edges and type C has parallel fin edges. The results show that type A devices have the largest SET variation while type C devices have the smallest variation. Further, the impact of the two main LER parameters,correlation length and root mean square amplitude, on SET variation is discussed as well. The results indicate that variation may be a concern in radiation effects with the down scaling of feature size.

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

With the critical charge reduced to generate a single event effect （SEE） and high working frequency for a nanometer integrated circuit, the single event effect （SET） becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n＋ guard ring and p＋ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient （SET） pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET＇s pulse- width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV-cm2/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LETefr from 12.5 MeV.cm2/mg to 79.5 MeV-cm2/mg and the pulse-width presents saturation tendency when the effective linear energy transfer （LETeff value is larger than 40 MeV-cm2/mg. The test results also show that the hardened commercial standard cell＇s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.

Single event transient characterization of SiGe HBT by SPA experiment and 3-D process simulation

The single-photon absorption induced single event transient in the silicon-germanium heterojunction bipolar transistor is investigated.The laser wavelength and bias condition have been proven to have significant impacts on the characterization of the single event transient(SET) response of the device by two-dimensional(2-D) raster scanning.After optical analytical calculation,the laser-induced charge distribution is well-embedded in the 3-D TCAD process simulation conducted to explore the underlying physical mechanism.In addition to the ion shunt effect,the excess electron injection from the emitter to the base could play a vital role in the SET peak amplitude and charge collection.The impact of the metal layer on the SPA experimental results is also determined by establishing a figure of merit that will help researchers estimate the laser-induced transient sensitivity of devices with metal layer blocking.

A single-event transient induced by a pulsed laser in a silicon-germanium heterojunction bipolar transistor

A study on the single event transient （SET） induced by a pulsed laser in a silicon-germanium （SiGe） heterojunction bipolar transistor （HBT） is presented in this work. The impacts of laser energy and collector load resistance on the SET are investigated in detail. The waveform, amplitude, and width of the SET pulse as well as collected charge are used to characterize the SET response. The experimental results are discussed in detail and it is demonstrated that the laser energy and load resistance significantly affect the SET in the SiGe HBT. Furthermore, the underlying physical mechanisms are analyzed and investigated, and a near-ideal exponential model is proposed for the first time to describe the discharge of laser-induced electrons via collector resistance to collector supply when both base-collector and collector-substrate junctions are reverse biased or weakly forward biased. Besides, it is found that an additional multi-path discharge would play an important role in the SET once the base-collector and collector-substrate junctions get strongly forward biased due to a strong transient step charge by the laser pulse.

Effect of charge sharing on the single event transient response of CMOS logic gates

This paper presents three new types of pulse quenching mechanism（NMOS-to-PMOS,PMOS-to-NMOS and NMOS-to-NMOS） and verifies them using 3-D TCAD mixed mode simulations at the 90 nm node. The three major contributions of this paper are：（1） with the exception of PMOS-to-PMOS,pulse quenching is also prominent for PMOS-to-NMOS and NMOS-to-NMOS in a 90 nm process.（2） Pulse quenching in general correlates weakly with ion LET,but strongly with incident angle and layout style（i.e.spacing between transistors and n-well contact area）.（3） Compact layout and cascaded inverting stages can be utilized to promote SET pulse quenching in combinatorial circuits.

The dual role of multiple-transistor charge sharing collection in single-event transients

As technologies scale down in size, multiple-transistors being affected by a single ion has become a universal phenomenon, and some new effects are present in single event transients （SETs） due to the charge sharing collection of the adjacent multiple-transistors. In this paper, not only the off-state p-channel metal–oxide semiconductor field-effect transistor （PMOS FET）, but also the on-state PMOS is struck by a heavy-ion in the two-transistor inverter chain, due to the charge sharing collection and the electrical interaction. The SET induced by striking the off-state PMOS is efficiently mitigated by the pulse quenching effect, but the SET induced by striking the on-state PMOS becomes dominant. It is indicated in this study that in the advanced technologies, the SET will no longer just be induced by an ion striking the off-state transistor, and the SET sensitive region will no longer just surround the off-state transistor either, as it is in the older technologies. We also discuss this issue in a three-transistor inverter in depth, and the study illustrates that the three-transistor inverter is still a better replacement for spaceborne integrated circuit design in advanced technologies.

The temperature dependence of single-event transients in 90-nm CMOS dual-well and triple-well NMOSFETs

This paper investigates the temperature dependence of single-event transients（SETs） in 90-nm complementary metat-oxide semiconductor（CMOS） dual-well and triple-well negative metal-oxide semiconductor field-effect transistors（NMOSFETs）.Technology computer-aided design（TCAD） three-dimensional（3D） simulations show that the drain current pulse duration increases from 85 ps to 245 ps for triple-well but only increases from 65 ps to 98 ps for dual-well when the temperature increases from-55℃ to 125℃,which is closely correlated with the NMOSFET sources.This reveals that the pulse width increases with temperature in dual-well due to the weakening of the anti-amplification bipolar effect while increases with temperature in triple-well due to the enhancement of the bipolar amplification.

Error Correction Circuit for Single-Event Hardening of Delay Locked Loops

In scaled CMOS processes, the single-event effects generate missing output pulses in Delay-Locked Loop (DLL). Due to its effective sequence detection of the missing pulses in the proposed Error Correction Circuit (ECC) and its portability to be applied to any DLL type, the ECC mitigates the impact of single-event effects and completes its operation with less design complexity without any concern about losing the information. The ECC has been implemented in 180 nm CMOS process and measured the accuracy of mitigation on simulations at LETs up to 100 MeV-cm2/mg. The robustness and portability of the mitigation technique are validated through the results obtained by implementing proposed ECC in XilinxArtix 7 FPGA.