Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of ^(209)Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

Recovery of single event upset in advanced complementary metal-oxide semiconductor static random access memory cells

Using computer-aided design three-dimensional （3D） simulation technology, the recovery mechanism of single event upset and the effects of spacing and hit angle on the recovery are studied. It is found that the multi-node charge collection plays a key role in recovery and shielding the charge sharing by adding guard rings. It cannot exhibit the recovery effect. It is also indicated that the upset linear energy transfer （LET） threshold is kept constant while the recovery LET threshold increases as the spacing increases. Additionally, the effect of incident angle on recovery is analysed and it is shown that a larger angle can bring about a stronger charge sharing effect, thus strengthening the recovery ability.

The supply voltage scaled dependency of the recovery of single event upset in advanced complementary metal-oxide-semiconductor static random-access memory cells

Using computer-aided design three-dimensional simulation technology,the supply voltage scaled dependency of the recovery of single event upset and charge collection in static random-access memory cells are investigated.It reveals that the recovery linear energy transfer threshold decreases with the supply voltage reducing,which is quite attractive for dynamic voltage scaling and subthreshold circuit radiation-hardened design.Additionally,the effect of supply voltage on charge collection is also investigated.It is concluded that the supply voltage mainly affects the bipolar gain of the parasitical bipolar junction transistor（BJT） and the existence of the source plays an important role in supply voltage variation.

Impact of energy straggle on proton-induced single event upset test in a 65-nm SRAM cell

This paper presents a simulation study of the impact of energy straggle on a proton-induced single event upset （SEU） test in a commercial 65-nm static random access memory cell. The simulation results indicate that the SEU cross sections for low energy protons are significantly underestimated due to the use of degraders in the SEU test. In contrast, using degraders in a high energy proton test may cause the overestimation of the SEU cross sections. The results are confirmed by the experimental data and the impact of energy straggle on the SEU cross section needs to be taken into account when conducting a proton-induced SEU test in a nanodevice using degraders.

Experimental study of temperature dependence of single-event upset in SRAMs

We report on the temperature dependence of single-event upsets in the 215–353 K range in a 4M commercial SRAM manufactured in a 0.15-lm CMOS process,utilizing thin film transistors. The experimental results show that temperature influences the SEU cross section on the rising portion of the cross-sectional curve(such as the chlorine ion incident). SEU cross section increases 257 %when the temperature increases from 215 to 353 K. One of the possible reasons for this is that it is due to the variation in upset voltage induced by changing temperature.

Azimuthal dependence of single-event and multiple-bit upsets in SRAM devices with anisotropic layout

Experimental evidence is presented showing obvious azimuthal dependence of single event upsets(SEU) and multiple-bit upset(MBU) patterns in radiation hardened by design(RHBD) and MBU-sensitive static random access memories(SRAMs), due to the anisotropic device layouts. Depending on the test devices, a discrepancy from 24.5% to 50% in the SEU cross sections of dual interlock cell(DICE) SRAMs is shown between two perpendicular ion azimuths under the same tilt angle. Significant angular dependence of the SEU data in this kind of design is also observed, which does not fit the inverse-cosine law in the effective LET method. Ion trajectory-oriented MBU patterns are identified, which is also affected by the topological distribution of sensitive volumes. Due to that the sensitive volumes are periodically isolated by the BL/BLB contacts along the Y-axis direction, double-bit upsets along the X-axis become the predominant configuration under normal incidence.Predominant triple-bit upset and quadruple-bit upset patterns are the same under different ion azimuths(Lshaped and square-shaped configurations, respectively). Those results suggest that traditional RPP/IRPP model should be promoted to consider the azimuthal and angular dependence of single event effects in certain designs.During earth-based evaluation of SEE sensitivity, worst case beam direction, i.e., the worst case response, should be revealed to avoid underestimation of the on-orbit error rate.

Pattern dependence in synergistic effects of total dose on single-event upset hardness

The pattern dependence in synergistic effects was studied in a 0.18 μm static random access memory（SRAM） circuit.Experiments were performed under two SEU test environments：3 Me V protons and heavy ions.Measured results show different trends.In heavy ion SEU test,the degradation in the peripheral circuitry also existed because the measured SEU cross section decreased regardless of the patterns written to the SRAM array.TCAD simulation was performed.TIDinduced degradation in n MOSFETs mainly induced the imprint effect in the SRAM cell,which is consistent with the measured results under the proton environment,but cannot explain the phenomena observed under heavy ion environment.A possible explanation could be the contribution from the radiation-induced GIDL in pMOSFETs.

A novel single event upset reversal in 40-nm bulk CMOS 6T SRAM cells

In advanced technologies, single event upset reversal(SEUR) due to charge sharing can make the upset state of SRAM cells recover to their initial state, which can reduce the soft error for SRAMs in radiation environments. By using the full 3D TCAD simulations, this paper presents a new kind of SEUR triggered by the charge collection of the Off-PMOS and the delayed charge collection of the On-NMOS in commercial 40-nm 6 T SRAM cells. The simulation results show that the proposed SEUR can not occur at normal incidence,but can present easily at angular incidence. It is also found that the width of SET induced by this SEUR remains the same after linear energy transfer(LET) increases to a certain value. In addition, through analyzing the effect of the spacing, the adjacent transistors, the drain area, and some other dependent parameters on this new kind of SEUR, some methods are proposed to strengthen the recovery ability of SRAM cells.

Strategy to mitigate single event upset in 14-nm CMOS bulk FinFET technology

Three-dimensional(3 D)TCAD simulations demonstrate that reducing the distance between the well boundary and N-channel metal-oxide semiconductor(NMOS)transistor or P-channel metal-oxide semiconductor(PMOS)transistor can mitigate the cross section of single event upset(SEU)in 14-nm complementary metal-oxide semiconductor(CMOS)bulk Fin FET technology.The competition of charge collection between well boundary and sensitive nodes,the enhanced restoring currents and the change of bipolar effect are responsible for the decrease of SEU cross section.Unlike dualinterlock cell(DICE)design,this approach is more effective under heavy ion irradiation of higher LET,in the presence of enough taps to ensure the rapid recovery of well potential.Besides,the feasibility of this method and its effectiveness with feature size scaling down are discussed.

Geant4 simulation of proton-induced single event upset in three-dimensional die-stacked SRAM device

Geant4 Monte Carlo simulation results of the single event upset(SEU)induced by protons with energy ranging from 0.3 MeV to 1 GeV are reported.The SEU cross section for planar and three-dimensional(3D)die-stacked SRAM are calculated.The results show that the SEU cross sections of the planar device and the 3D device are different from each other under low energy proton direct ionization mechanism,but almost the same for the high energy proton.Besides,the multi-bit upset(MBU)ratio and pattern are presented and analyzed.The results indicate that the MBU ratio of the 3D die-stacked device is higher than that of the planar device,and the MBU patterns are more complicated.Finally,the on-orbit upset rate for the 3D die-stacked device and the planar device are calculated by SPACE RADIATION software.The calculation results indicate that no matter what the orbital parameters and shielding conditions are,the on-orbit upset rate of planar device is higher than that of 3D die-stacked device.

Simulation of temporal characteristics of ion-velocity susceptibility to single event upset effect

Using a Monte Carlo simulation tool of the multi-functional package for SEEs Analysis （MUFPSA）, we study the temporal characteristics of ion-velocity susceptibility to the single event upset （SEU） effect, including the deposited energy, traversed time within the device, and profile of the current pulse. The results show that the averaged dposited energy decreases with the increase of the ion-velocity, and incident ions of 2~9Bi have a wider distribution of energy deposition than 132Xe at the same ion-velocity. Additionally, the traversed time presents an obvious decreasing trend with the increase of ion-velocity. Concurrently, ion-velocity certainly has an influence on the current pulse and then it presents a particular regularity. The detailed discussion is conducted to estimate the relevant linear energy transfer （LET） of incident ions and the SEU cross section of the testing device from experiment and simulation and to critically consider the metric of LET.

Synergistic effects of total ionizing dose on single event upset sensitivity in static random access memory under proton irradiation

Synergistic effects of the total ionizing dose （TID） on the single event upset （SEU） sensitivity in static random access memories （SRAMs） were studied by using protons. The total dose was cumulated with high flux protons during the TID exposure, and the SEU cross section was tested with low flux protons at several cumulated dose steps. Because of the radiation-induced off-state leakage current increase of the CMOS transistors, the noise margin became asymmetric and the memory imprint effect was observed.

Neutron-induced single event upset simulation in Geant4 for three-dimensional die-stacked SRAM

Three-dimensional integrated circuits(3D ICs)have entered into the mainstream due to their high performance,high integration,and low power consumption.When used in atmospheric environments,3D ICs are irradiated inevitably by neutrons.In this paper,a 3D die-stacked SRAM device is constructed based on a real planar SRAM device.Then,the single event upsets(SEUs)caused by neutrons with different energies are studied by the Monte Carlo method.The SEU cross-sections for each die and for the whole three-layer die-stacked SRAM device is obtained for neutrons with energy ranging from 1 MeV to 1000 MeV.The results indicate that the variation trend of the SEU cross-section for every single die and for the entire die-stacked device is consistent,but the specific values are different.The SEU cross-section is shown to be dependent on the threshold of linear energy transfer(LETth)and thickness of the sensitive volume(Tsv).The secondary particle distribution and energy deposition are analyzed,and the internal mechanism that is responsible for this difference is illustrated.Besides,the ratio and patterns of multiple bit upset(MBU)caused by neutrons with different energies are also presented.This work is helpful for the aerospace IC designers to understand the SEU mechanism of 3D ICs caused by neutrons irradiation.

Influences of supply voltage on single event upsets and multiple-cell upsets in nanometer SRAM across a wide linear energy transfer range

The influences of reducing the supply voltage on single event upset(SEU) and multiple-cell upset(MCU) in two kinds of 65-nm static random access memories(SRAMs) are characterized across a wide linear energy transfer(LET) range.The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6 T SRAM or radiation-hardened double dual interlocked cells(DICE) SRAM.When the LET value is lower than the LET threshold of MCU,the SEU only manifests single cell upset,the SEU cross section increases with the decrease of voltage.The lower the LET value,the higher the SEU sensitivity to the voltage variation is.Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU.Moreover,the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range.With further scaling the feature size of devices down,it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf(COTS) SRAM.

基于双核锁步的多核处理器SEU加固方法

以单粒子翻转为代表的软错误是制约COTS器件空间应用的主要因素之一;为了满足空间应用对高集成卫星电子系统抗辐照防护的要求,提出了一种面向通用多核处理器的单粒子翻转加固方法,通过软件层面双核互检,在不额外增加硬件开销的前提下,充分提高了COTS器件的可靠性,具有良好的可移植性和较强的工程实用价值;进行软件故障注入实验,在程序执行的关键节点注入错误信息,验证该双核互检方法实用性;实验结果表明双核互锁方法可以100%检测出系统中产生的单粒子翻转,抗软错误能力满足应用需要。

Ionizing radiation effect on single event upset sensitivity of ferroelectric random access memory

The impact of ionizing radiation effect on single event upset（SEU） sensitivity of ferroelectric random access memory（FRAM） is studied in this work. The test specimens were firstly subjected to ^60Co γ-ray and then the SEU evaluation was conducted using ^209Bi ions. As a result of TID-induced fatigue-like and imprint-like phenomena of the ferroelectric material, the SEU cross sections of the post-irradiated devices shift substantially. Different trends of SEU cross section with elevated dose were also found, depending on whether the same or complementary test pattern was employed during the TID exposure and the SEU measurement.

3-20 Heavy Ion Induced Single Event Upset in a Harden SOI SRAM

In order to deepen the understanding of the difference between 0 ! 1 and 1 ! 0 sinle event upset (SEU)cross-section in a novel active delay element (ADE) SRAM (Static Random Access Memory) cell, the irradiationwas carried out at Heavy Ion Research Facility in Lanzhou (HIRFL). Using the 86Kr26+ ions irradiated the deviceunder test (DUT) adopted partially depleted (PD) silicon of insulator (SOI) technology. The feature size of DUTfabricated by institute of microelectronic (IME) was 180 nm. The schematic diagram of SEU harden ADE-SRAMcell is shown in Fig. 1. The ADE is essentially a NMOS connected in only one of the feedback paths between thetwo inventors of the memory cell. It plays a role as switching transistor. Except during a write operation, whenthe switch transistor is turned on (so as not to compromise the write speed), the off-ADE provides a much greaterRC delay between the two inventors of the memory cell to achieve much improved SEU hardness[1].

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

卷积神经网络加速器中SEU的评估与加固研究

AI加速器在空间探索应用时需要考虑到空间辐射环境下SEE引发的软错误。在AI加速器设计过程中,需要对其SEE容错能力和可靠性进行评估,本文对Lenet-5的加速器进行了SEU故障注入,提出了一种从网络结构与电路模块映射的角度进行统计评估的方法。实验结果证明,在神经网络中,由于AI加速器计算数据大的特点,发生在权重和特征图的SEU错误在传播过程中有可能会被池化层屏蔽掉,SEU错误发生在靠近输出的层级比靠近输入的层级更容易导致识别准确率的下降。此外,实验还发现,在加速器电路模块映射中,负责产生使能信号和地址控制信号的控制单元CTRL比处理单元PE和存储单元MEM更容易被SEU错误所影响,严重时会影响加速器的正常运行。最后本文针对评估结果,进行了STMR加固措施对CTRL进行了加固,相比于FTMR,极大地减少了面积开销。

NMOS晶体管电荷共享导致的SRAM单元单粒子翻转恢复效应研究

基于Synopsys公司的三维器件模拟软件TCAD,本文研究了NMOS晶体管电荷共享导致SRAM单元的单粒子翻转恢复(SEUR)效应。分析了NMOS晶体管电荷共享导致SEUR效应的物理机制,系统研究了NMOS晶体管偏置(如电源电压、P阱偏置电压)和工艺参数(如P+深阱掺杂浓度、P阱接触距离)对线性能量传输翻转恢复阈值(LETrec)以及单粒子翻转脉冲宽度(PWrec)的影响。研究发现:PWrec随着电源电压的增大而增大;PWrec和LETrec随着P阱偏置电压的增大而减小;LETrec随着P+深阱掺杂浓度的增大而增大;PWrec随着P阱接触与NMOS晶体管之间距离的增大而增大,而LETrec随着P阱接触与NMOS晶体管之间距离增大而减小。本文研究结论有助于优化SRAM单元抗单粒子效应设计,尤其是基于SEUR效应的SRAM单元的抗辐照加固设计提供了理论指导。