A novel single event upset reversal in 40-nm bulk CMOS 6T SRAM cells

In advanced technologies, single event upset reversal(SEUR) due to charge sharing can make the upset state of SRAM cells recover to their initial state, which can reduce the soft error for SRAMs in radiation environments. By using the full 3D TCAD simulations, this paper presents a new kind of SEUR triggered by the charge collection of the Off-PMOS and the delayed charge collection of the On-NMOS in commercial 40-nm 6 T SRAM cells. The simulation results show that the proposed SEUR can not occur at normal incidence,but can present easily at angular incidence. It is also found that the width of SET induced by this SEUR remains the same after linear energy transfer(LET) increases to a certain value. In addition, through analyzing the effect of the spacing, the adjacent transistors, the drain area, and some other dependent parameters on this new kind of SEUR, some methods are proposed to strengthen the recovery ability of SRAM cells.

SRAM单元SEUR脉冲宽度缩减的工艺优化方法研究

集成电路中电荷共享效应引起的多节点电荷收集在当前成为集成电路发生软错误的主要原因,然而在存储单元如SRAM中可以通过晶体管布局利用电荷共享效应将SRAM单元发生的单粒子翻转效应进行恢复。本文基于三维器件物理仿真软件对65 nm体硅CMOS工艺SRAM单元进行混合仿真,通过调节工艺参数和晶体管布局的方法研究了SRAM单元单粒子翻转恢复(SEUR)效应的特性。研究结果表明,将PMOS晶体管布局在靠近P阱/N阱边界处的位置和增加N阱深度可以减少N阱中空穴的排出量,进而提升N阱电势,抑制了器件内部的寄生双极效应,最终缩减了SRAM单元的SEUR脉冲宽度,降低了SRAM单元发生单粒子翻转的概率。该研究结果对集成电路存储单元抗辐射加固具有一定的指导意义。